High-Voltage Semiconductor Structure for Gate Leakage Prevention
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Solution Overview
Problem
High-voltage semiconductor devices face challenges in sustaining high voltage surges, leading to issues like gate leakage, which is not allowable in certain applications, due to the complexity and vulnerability of modern semiconductor devices.
Innovation Solution
The semiconductor device design incorporates a p-type substrate with field isolation layers and a polysilicon layer acting as a field plate to enhance the drain-to-source breakdown voltage and prevent gate leakage by ensuring the gate voltage does not exceed the source voltage, using a thick field isolation layer and multiple p-type bottom layers to control the electric field distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the semiconductor device is designed for high-voltage operation, then the breakdown voltage is improved, but gate leakage occurs
Solution Approach 1:
A thick field isolation layer (first field isolation layer) is introduced as an intermediary between the gate electrode and the source/drain regions. This field isolation layer acts as a mediator that controls and distributes the electric field, preventing direct high-voltage stress on the gate while maintaining the high breakdown voltage capability of the device.
Solution Approach 2:
The patent changes the thickness parameter of the field isolation layer to be greater than a predetermined threshold value. This parameter change transforms the field isolation layer's ability to withstand electric field stress, enabling it to prevent gate leakage while maintaining high breakdown voltage. The doping concentration of the p-type bottom layer is also adjusted to optimize electric field distribution.
2Speed
If modern semiconductor devices are made more complex for high-speed computation and compact size, then computation speed and product size are improved, but vulnerability to voltage surges increases
Solution Approach 1:
The patent implements a protective structure consisting of a thick field isolation layer and a p-type bottom layer with specific doping characteristics before voltage surge events occur. This pre-configured protective structure acts as a cushion that absorbs and distributes voltage surge stress, preventing damage to the gate electrode and other sensitive components during high-voltage events.
3Power
If input or output pins are designed to sustain tremendous voltage or current surges, then power operation capability is improved, but the semiconductor devices connected to these pins face structural challenges
Solution Approach 1:
The patent applies different doping concentrations and structural characteristics to different regions of the semiconductor device. The p-type bottom layer has a doping concentration that differs from the substrate, and the field isolation layer has specific thickness characteristics. This local differentiation of properties allows the device to sustain high voltage surges at critical regions while maintaining overall structural efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively prevents gate leakage and enhances the breakdown voltage, ensuring reliable operation under high-voltage conditions without current surges from the gate to the source, thus addressing the vulnerability of semiconductor devices to voltage surges.
Implementation Method 1
using a thick field isolation layer and multiple p-type bottom layers to control the electric field distribution
Data Source
AI summary
High-voltage semiconductor devices are disclosed, each having gate, source and drain electrodes. A deep well layer is formed on a substrate and has a surface, where the substrate and the deep well layer are of first-type and second-type conductivities, respectively. A field isolation layer on the surface isolates a drain active region from a source active region. The source electrode contacts the source active region on the surface to form an ohmic contact. The drain electrode contacts the drain active region on the surface. A first well layer of the first-type conductivity is formed on the surface and between the ohmic contact and the drain active region, and at least a portion of the first well layer is under the field isolation layer. A bottom layer of the first-type conductivity is formed at a bottom of the deep well layer. The gate electrode is on the field isolation layer.