High-Voltage FinFET Gate Oxide Integration Using ILD Layers
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Solution Overview
Problem
High-voltage fin-based transistors face challenges in achieving sufficient gate isolation and reduced processing complexity due to the need for additional processing steps and potential gate leakage issues, particularly in PMOS and NMOS transistors where the reduced area between the gate oxide layer and the BEOL layer increases the likelihood of breakdown voltage reduction.
Innovation Solution
Configuring interlayer dielectric (ILD) layers as the gate oxide for high-voltage fin-based PMOS and NMOS transistors, eliminating the need for dedicated gate oxide layers and utilizing middle-end-of-line (MEOL) structures or BEOL layers as gate contacts to tune work functions, thereby reducing processing complexity and enhancing gate oxide thickness for improved isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If larger gate oxide layers are used in high-voltage fin-based transistors, then gate isolation is improved, but breakdown voltage is reduced and gate leakage is increased
Solution Approach 1:
The patent merges the gate oxide function with the interlayer dielectric (ILD) layer by configuring the ILD layer to serve as the gate oxide for high-voltage PMOS and NMOS transistors. This eliminates the need for a separate dedicated gate oxide deposition process, thereby maintaining sufficient gate oxide thickness to prevent leakage while avoiding the harmful effects of thinner oxide layers. The gate contact and BEOL layers are configured as work function layers to complete the gate structure without requiring additional oxide deposition.
2Manufacturing precision
If dedicated gate oxide deposition is performed, then gate oxide thickness can be controlled, but processing complexity and cost increase
Solution Approach 1:
The patent applies universality by making the interlayer dielectric (ILD) layer serve multiple functions: it acts as both the interlayer insulation layer and the gate oxide for high-voltage transistors. This multi-functional approach eliminates the need for a separate dedicated gate oxide deposition process, thereby reducing processing complexity and cost while still allowing precise control of the effective gate oxide thickness through the ILD layer configuration.
Solution Approach 2:
The patent combines the gate oxide deposition step with the existing ILD layer formation process. By configuring the ILD layer to function as the gate oxide, the patent merges two previously separate processes into one, thereby reducing the total number of deposition steps and simplifying the manufacturing workflow without sacrificing thickness control.
3Reliability
If dedicated gate oxide layers are deposited, then gate isolation can be ensured, but manufacturing cost and processing time increase
Solution Approach 1:
The patent merges the gate oxide function into the existing ILD layer formation process, eliminating the need for a separate dedicated gate oxide deposition step. This integration maintains sufficient gate oxide thickness to ensure reliable isolation while reducing the total number of processing steps, thereby improving manufacturing efficiency and productivity.
Solution Approach 2:
The patent makes the ILD layer universal by having it serve as both the interlayer dielectric and the gate oxide for high-voltage transistors. This multi-functional approach ensures that gate isolation is maintained without requiring additional processing steps, thereby reducing manufacturing cost and improving productivity.
Data Source
AI summary
Interlayer dielectric (ILD) layer(s) of a semiconductor device may be configured as a gate oxide for high-voltage transistors, and therefore additional process operations to deposit dedicated gate oxide layers are not needed. Moreover, additional processing operations to form the gate structures of the high-voltage fin-based PMOS transistors and high-voltage fin-based NMOS transistors are not needed in that middle end of line (MEOL process and back end of line (BEOL) processes can be used as the gate formation process of the high-voltage transistors.