High-Voltage Transistor Gate Structure Using Interconnect-Level Oxide
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor transistors face challenges in sustaining high voltages while adhering to the downsizing requirements of advanced processes, as the gate thickness exceeds the dielectric layer thickness, leading to insulation issues and complex manufacturing processes.
Innovation Solution
The use of an insulating layer as a gate oxide that is thicker than the gate oxide of existing transistors, integrated with a patterned conductive layer as part of the interconnection layer, allowing for simplified manufacturing and maintaining breakdown voltage performance without altering the well design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate oxide thickness is increased to sustain high voltages, then the breakdown voltage performance is improved, but the device complexity increases and manufacturing becomes more difficult
Solution Approach 1:
The patent combines the gate oxide layer with the interconnection layer structure by forming the gate electrode directly within the interconnection layer material. This merging eliminates the need for separate gate oxide deposition and patterning steps, reducing manufacturing complexity while maintaining the required gate oxide thickness for high voltage operation. The gate electrode is formed as part of the metal layer stack, integrating multiple functions into a single structural element.
Solution Approach 2:
The interconnection layer serves multiple functions: it acts as both the electrical interconnection medium and as the gate electrode structure. By making the interconnection layer material serve dual purposes, the patent eliminates the need for additional dedicated gate electrode materials and simplifies the overall device architecture. The same material layer provides both interconnect functionality and gate control functionality.
2Reliability
If the gate oxide thickness is increased to sustain high voltages, then the breakdown voltage performance is improved, but the manufacturing process becomes more complex
Solution Approach 1:
The patent merges the gate electrode formation process with the interconnection layer deposition process. The gate electrode is formed simultaneously with the interconnection layer using the same deposition and patterning steps, eliminating separate manufacturing operations. This integration maintains thick gate oxide for high voltage while avoiding additional process complexity.
Solution Approach 2:
The patent segments the gate structure formation into the interconnection layer deposition sequence, where the gate electrode is defined as a specific region within the metal layer stack. This segmentation allows the thick gate oxide to be formed as part of the standard interconnection process flow, avoiding the need for separate gate oxide processing steps.
3Reliability
If the gate thickness exceeds the dielectric layer thickness, then high voltage capability is achieved, but insulation issues arise
Solution Approach 1:
The patent introduces a dielectric layer positioned between the gate electrode and the active region to provide electrical isolation. This intermediary dielectric layer prevents direct electrical contact and potential shorting between the thick gate electrode structure and the underlying active region, resolving the insulation issues that would otherwise arise from the gate thickness exceeding the original gate oxide thickness.
Data Source
AI summary
A method of manufacturing a semiconductor device, including: forming a dielectric layer configured to be a gate oxide contacting the second well on the substrate, wherein the dielectric layer is single-layered dielectric layer and includes a contact via penetrating through the dielectric layer; and forming a patterned conductive layer contacting the dielectric layer, wherein the patterned conductive layer includes a first conductive portion isolated from the second well and configured to be a gate electrode, and a second conductive portion coupled to the first well via the contact via; wherein the first conductive portion is leveled with the second conductive portion, and the first conductive portion and the second conductive portion are formed entirely on a topmost surface of the dielectric layer; wherein the dielectric layer and the first conductive portion collectively serve as a gate of the transistor, and the transistor is configured as a high-voltage transistor.