High Voltage Generator for Semiconductor Memory Devices
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in achieving high-speed erase, program, and read operations due to limitations in high voltage generation, particularly in NAND-type memory devices, where ramping up high voltage takes time and consumes power, affecting performance.
Innovation Solution
A semiconductor memory device with a high voltage generator that provides continuous high voltage levels to word lines and bit lines, using a bit line decoder to sequentially charge and discharge bit lines, and a current flow control device to decouple high voltage nodes, along with dynamic and static reference cells and sensing circuits to optimize high voltage operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If drain pumps with large capacitors are used to generate high voltage, then high voltage and high current are provided for memory operations, but the device takes time to ramp up to targeted high voltage level
Solution Approach 1:
The high voltage generator continuously maintains high voltage at the high voltage supply node before it is needed for bit line operations. This preliminary action ensures that when bit lines require high voltage, it is immediately available without ramping delays, thus resolving the contradiction between providing high power and minimizing time loss.
Solution Approach 2:
The invention implements continuous high voltage generation and maintenance at the high voltage supply node, rather than intermittent generation. This continuity ensures that high voltage is always ready for immediate use during memory operations, eliminating the ramping time that would otherwise be required and resolving the time-power contradiction.
2Power
If conventional high voltage generating devices are used, then high voltage is provided for memory operations, but the device cannot provide erase, program and read operations of sufficient speed to operate as NAND-type memories
Solution Approach 1:
By continuously maintaining high voltage at the supply node in advance, the system eliminates the startup delay that would otherwise limit operation speed. This preliminary preparation of high voltage enables immediate execution of erase, program, and read operations at full speed, resolving the contradiction between providing sufficient power and achieving high productivity.
Solution Approach 2:
The continuous operation of the high voltage generator ensures that high voltage is perpetually available, removing any interruption or delay in the memory operation cycle. This continuity enables the memory device to operate at maximum speed for all operations, resolving the speed limitation imposed by conventional ramping-based high voltage generation.
3Reliability
If high voltage is continuously provided to bit lines, then high voltage operations are maintained, but power consumption increases
Solution Approach 1:
The bit line decoder is divided into multiple independent sections, each capable of being controlled separately. This segmentation allows high voltage to be applied only to the specific section currently being accessed, rather than continuously to all bit lines, thus maintaining reliable high voltage operation while significantly reducing overall power consumption.
Solution Approach 2:
High voltage is applied locally only to the specific bit line section that requires it for the current operation, rather than globally to all bit lines. This localized application maintains the reliability of high voltage operations where needed while minimizing power consumption in sections that do not currently require high voltage.
Data Source
AI summary
A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710). For additional improvements to program operations, the high voltage generator (106) decouples high voltages provided to the word lines (502) and the bit lines (504) by providing a current flow control device (1208) therebetween and provides a boosting voltage at a time (1104) to overcome a voltage level drop (1102) resulting from a capacitor load associated with selected bit lines (504) and/or the bit line decoder (120) precharges (1716) a second portion of the bit lines (504) while providing a high voltage level to a first portion to program (1706) a first portion of memory cells (200). For improvements to read operations, whether dynamic reference cells (2002) are blank is determined by providing non-identically regulated high voltage levels from a first voltage source (2112) to the dynamic reference cells (2002) and from a second voltage source (2104) to static reference cells (2004) and, if the dynamic reference cells (2002) are not blank, reads selected memory cells (200) by providing identically regulated high voltage levels to the selected memory cells (200), the dynamic reference cells (2002) and the static reference cells (2004).