High Voltage III-Nitride HEMT with Opposite Polarity Silicon Substrate
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Solution Overview
Problem
Conventional III-nitride semiconductor devices face challenges in maintaining optimal charge carrier constraint within the conduction zone under high applied voltages, leading to potential device failure and inability to handle high voltages effectively, especially when charge carriers disperse into the silicon substrate.
Innovation Solution
The implementation of a high voltage durability III-nitride semiconductor device is achieved by using a silicon substrate with a conductivity type opposite to that of the majority charge carriers, ensuring enhanced resistance to breakdown, and enabling monolithic vertical integration with silicon devices through a specific layer structure and doping configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional III-nitride semiconductor device fabrication approaches are used, then device fabrication is simplified, but charge carrier constraint within the conduction zone deteriorates under high voltage
Solution Approach 1:
The device is segmented into multiple functional layers including a silicon substrate, buffer layer, first III-nitride layer, second III-nitride layer, and contact layers. This segmentation allows each layer to perform its specific function: the silicon substrate provides mechanical support and opposite polarity doping, the buffer layer manages dislocation, and the III-nitride layers form the conduction channel with proper charge carrier constraint.
Solution Approach 2:
Different regions of the device are doped with different polarities at different locations. The silicon substrate is doped with polarity opposite to the majority charge carriers in the conduction layer, while specific contact layers are doped to provide proper electrical contact. This local quality variation ensures optimal charge carrier constraint in the conduction zone while maintaining ease of fabrication through standard doping processes.
2Power
If high applied voltage is applied to the device, then power handling capability is improved, but charge carriers disperse into the silicon substrate causing device failure
Solution Approach 1:
The silicon substrate is pre-doped with a polarity opposite to the majority charge carriers in the conduction layer before the device is put into operation. This preliminary anti-action creates an electric field that repels charge carriers from dispersing into the substrate, preventing breakdown even when high voltages are applied. The opposite polarity doping acts as a preventive measure against charge carrier dispersion.
Solution Approach 2:
The device structure includes a buffer layer and specifically designed contact layers that act as protective barriers before charge carriers can reach the silicon substrate. These layers provide beforehand cushioning by managing dislocation and controlling charge carrier flow, preventing direct interaction between high-energy charge carriers and the substrate that would cause breakdown.
3Ease of manufacture
If the silicon substrate conductivity type matches the majority charge carrier polarity, then fabrication is easier, but voltage breakdown resistance decreases
Solution Approach 1:
Instead of using a silicon substrate with the same polarity as the majority charge carriers (which would be conventional), the invention inverts this approach by using a silicon substrate doped with opposite polarity. This inversion creates a beneficial effect where the opposite polarity substrate prevents charge carrier dispersion and increases breakdown voltage, while still allowing standard silicon fabrication processes to be used.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly enhances the device's ability to withstand high voltages (up to 1200 volts) and supports the integration of III-nitride and silicon devices, ensuring reliable operation and improved performance in high voltage applications.
Implementation Method 1
the ability of a HEMT, or any III-nitride semiconductor device, to perform reliably in the face of a high applied voltage (e.g. voltage greater than 600 volts), depends in part on the charge retention characteristics of the 2DEG or other type of conduction channel. In particular, where charge carriers are insufficiently constrained from dispersing out of a desired conduction zone, for example by movement into a silicon substrate of the device
Implementation Method 2
a two-dimensional electron gas (2DEG) is generated at a semiconductor heterojunction. The 2DEG represents a very thin conduction layer of highly mobile and highly concentrated charge carriers free to move readily in the two dimensions of that conduction layer, but constrained from movement in a third dimension perpendicular to the conduction layer
Data Source
AI summary
A high voltage durability III-nitride semiconductor device comprises a support substrate including a first silicon body, an insulator body over the first silicon body, and a second silicon body over the insulator body. The high voltage durability III-nitride semiconductor device further comprises a III-nitride semiconductor body characterized by a majority charge carrier conductivity type, formed over the second silicon body. The second silicon body has a conductivity type opposite the majority charge carrier conductivity type. In one embodiment, the high voltage durability III-nitride semiconductor device is a high electron mobility transistor (HEMT) comprising a support substrate including a <100> silicon layer, an insulator layer over the <100> silicon layer, and a P type conductivity <111> silicon layer over the insulator layer. The high voltage durability HEMT also comprises a III-nitride semiconductor body formed over the P type conductivity <111> silicon layer, the III-nitride semiconductor body forming a heterojunction of the HEMT.