High-Voltage Tolerant Input Circuit Without Native Pass Gates
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Solution Overview
Problem
Existing electronic devices face challenges in interfacing different voltage domains with high voltage tolerance while maintaining operation at lower supply voltages, often resulting in inefficiencies such as static current flow and increased costs due to complex designs and the need for additional control signals or native devices.
Innovation Solution
A high-voltage tolerant circuit is implemented using parallel NMOS and PMOS transistors, with specific gate and substrate couplings, and an optional clamping transistor to manage voltage levels and prevent static current, allowing operation across various voltage levels without native devices and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a native pass gate is used to interface voltage domains, then high voltage tolerance is achieved, but device cost increases significantly and not all process technologies support native devices
Solution Approach 1:
The circuit is divided into multiple standard transistors (first NMOS, first PMOS, second NMOS, second PMOS) working in parallel and sequence, replacing the need for a single native pass gate. This segmentation allows standard process technologies to be used while achieving the same voltage tolerance function.
Solution Approach 2:
The parallel combination of standard NMOS and PMOS transistors creates a universal interface circuit that can handle both high voltage signals and low voltage operation. The circuit serves multiple functions: voltage level translation, high voltage tolerance, and low power consumption, without requiring process-specific native devices.
2Reliability
If a source follower configuration with resistor is used for high voltage tolerance, then high voltage tolerance is achieved, but constant static current flows creating power inefficiency
Solution Approach 1:
The circuit uses dynamic control of transistor gates to enable/disable current paths based on input signal conditions. The second NMOS and second PMOS transistors are controlled to prevent static current flow while maintaining high voltage tolerance, making the power consumption dynamic rather than constant.
Solution Approach 2:
The resistive element that causes constant static current in source follower configurations is removed. Instead, the patent uses purely transistor-based switching mechanisms to achieve voltage translation and high voltage tolerance without the continuous power dissipation associated with resistors.
3Reliability
If a switch CMOS pass gate is used for 5V tolerant input, then high voltage tolerance is achieved, but circuit complexity increases and additional control signals are required
Solution Approach 1:
Multiple transistor functions are merged into a compact parallel configuration. The first NMOS and first PMOS work together for primary voltage translation, while the second NMOS and second PMOS provide additional high voltage protection, all within a single unified circuit block without requiring separate control signal paths.
Solution Approach 2:
The circuit uses the input signal itself to control the switching action through the transistor gate connections. The parallel NMOS-PMOS configuration automatically activates appropriate current paths based on the input voltage level, eliminating the need for external control signals while maintaining high voltage tolerance.
4Speed
If voltage translation circuit with bootstrap circuit is used, then voltage translation speed is improved, but additional transistors and circuit area are required
Solution Approach 1:
The patent optimizes the local characteristics of each transistor in the parallel configuration to enable fast switching. The gate connections are strategically designed so that each transistor can rapidly respond to voltage changes, achieving fast voltage translation without requiring additional bootstrap capacitors or control circuits that would increase area.
Data Source
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AI summary
An electronic device is provided with a high- voltage tolerant circuit. The high- voltage tolerant circuit comprises an input terminal for receiving an input signal (VIN), a first node (A) and a second node (B), wherein the second node (B) is coupled to an input of a receiver (R). The high- voltage tolerant circuit furthermore comprises a first NMOS transistor (Nl) and a first PMOS transistor (Pl) coupled in parallel between the input terminal and the second node (B). Furthermore, a second PMOS transistor (P2) is coupled between the input terminal and node A and a second NMOS transistor is coupled with one of its terminals to the first node. The gate of the first NMOS transistor (N2) is coupled to a supply voltage (VDDE). The gate of the first PMOS transistor (Pl) is coupled to the first node (A). The gate of the second NMOS transistor (N2) and the gate of the second PMOS transistor (P2) are coupled to the supply voltage (VDDE).