High Voltage I/O Circuit ESD Protection via Clamping
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Solution Overview
Problem
Conventional high input voltage tolerant input/output circuits are vulnerable to electrostatic discharge (ESD) voltage, leading to damage of NMOS transistors when high voltages are applied, particularly during ESD testing.
Innovation Solution
The proposed solution includes a clamping circuit with a bias unit of serially connected diodes, resistors, and an NMOS transistor, as well as a buffer unit with PMOS and NMOS transistors, which generates a clamping signal to protect the NMOS transistors from ESD by turning them off during high voltage conditions, preventing damage from both positive and negative ESD voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the gate of the first NMOS transistor is connected to the power supply voltage VDD to enable high voltage tolerance, then the circuit can handle 5V input signals, but the gate oxide film is destroyed when ESD voltage is applied
Solution Approach 1:
A clamping circuit is introduced as an intermediary component between the pad and the buffer unit. This clamping circuit includes a P-N diode and an N-P diode that actively clamp the voltage at the pad to prevent ESD voltage from reaching the gate of the first NMOS transistor, thus protecting the gate oxide film while allowing high voltage operation
Solution Approach 2:
The clamping circuit performs preliminary protection by detecting and clamping ESD voltage before it can damage the NMOS transistor. The P-N diode and N-P diode are positioned to preemptively prevent voltage spikes from reaching sensitive components, countering the harmful ESD effect before it occurs
2Reliability
If the clamping circuit uses a P-N diode and N-P diode to protect against ESD, then ESD voltage is clamped, but the circuit complexity increases
Solution Approach 1:
The clamping circuit serves multiple functions: it protects against both positive and negative ESD voltage, enables high voltage tolerance, and maintains signal integrity. By combining these protective functions into a single integrated circuit block with standardized components, the overall system complexity is managed despite the added protection capabilities
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The circuit effectively prevents NMOS transistor damage by diverting ESD currents away from the transistors, ensuring stability under both normal and abnormal voltage conditions, including ESD scenarios.
Implementation Method 1
when an electrostatic discharge (ESD) voltage of several hundreds or thousands of Volts is applied to the pad 10 during a test for ESD voltage
Implementation Method 2
a first bias unit including a plurality of diodes serially connected to the power supply voltage
Data Source
AI summary
A high input voltage tolerant input/output circuit includes a pad, a clamping circuit clamping a high voltage applied to the pad to generate a clamping signal, and a buffer unit transmitting an input signal received by the pad to an internal circuit and outputting data of the internal circuit to the pad in response to the clamping signal. The buffer unit includes stacked NMOS transistors. When a high voltage higher than a power supply voltage is applied to the pad, the stacked NMOS transistors are turned on, and the stacked NMOS transistors are prevented from being destroyed by the high voltage. When an electrostatic discharge voltage is applied to the pad, the stacked NMOS transistors are turned off, and the stacked NMOS transistors are prevented from being destroyed by electrostatic discharge current.