High-Voltage Tolerant I/O Circuit for Power-Off Chip Protection
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Solution Overview
Problem
Traditional I/O circuits in electronic devices are vulnerable to external high voltages when the internal chip's core voltage is turned off, leading to potential damage and malfunction due to the inability of protection circuits to operate in such scenarios.
Innovation Solution
A high voltage tolerant I/O circuit design that includes a voltage reducing circuit, a first node, transistors, and control logic to generate a reduced voltage from external signals, allowing the circuit to operate effectively even when the internal voltage is lower than the external voltage, thereby protecting the internal chip from electrical over stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional protection circuit is used in the I/O circuit, then the internal chip is protected from external voltage damage during normal operation, but the protection circuit cannot operate when the internal voltage is turned off, leaving the I/O circuit vulnerable to external high voltage
Solution Approach 1:
The patent introduces a voltage reducing circuit as an intermediary component between the signal pad and the I/O circuit. This circuit generates a reduced voltage from the internal voltage that can operate independently even when the main internal voltage is turned off. The reduced voltage serves as a mediator to activate the protection circuit during low-power states, solving the contradiction between protection capability and operational status.
Solution Approach 2:
The patent implements preliminary action by pre-configuring the voltage reducing circuit to generate a reduced voltage that is specifically designed to activate the protection circuit before any external high voltage damage can occur. This reduced voltage is prepared in advance and can immediately respond to external voltage threats even when the main system is in a low-power state.
2Reliability
If the internal operating voltage is reduced to protect the internal chip, then the chip reliability is improved, but the I/O circuit cannot tolerate external voltages higher than the reduced internal voltage
Solution Approach 1:
The voltage reducing circuit acts as an intermediary that transforms the external high voltage into a reduced voltage level that the internal chip can tolerate. This intermediary component allows the I/O circuit to interface with external high voltage signals while protecting the internal chip by presenting only a reduced, safe voltage level to the chip's input terminals.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting the voltage level parameter. The voltage reducing circuit changes the voltage parameter from a high external voltage level to a lower internal voltage level that the chip can withstand. This parameter transformation enables the I/O circuit to tolerate external voltages higher than the internal operating voltage without damaging the chip.
3Object-affected harmful factors
If the I/O circuit is designed to tolerate external high voltage, then the external voltage damage is prevented, but additional protection circuits increase the overall circuit complexity
Solution Approach 1:
The voltage reducing circuit serves multiple functions: it reduces voltage levels for chip protection, activates the protection circuit during low-power states, and provides a stable operating voltage for the I/O circuit. By making this single circuit multi-functional, the patent achieves comprehensive voltage protection without proportionally increasing circuit complexity.
Solution Approach 2:
The patent merges the voltage reducing function with the protection circuit activation function into a single integrated solution. The voltage reducing circuit is combined with the existing I/O circuit architecture, sharing components and functionality to minimize the increase in overall circuit complexity while achieving enhanced voltage tolerance.
Data Source
AI summary
A high voltage tolerant I/O circuit of an electronic device is disclosed, including a voltage reducing circuit, a first node, a first transistor, a second transistor, and a control logic. The voltage reducing circuit is coupled with a signal pad and utilized for generating a reduced voltage according to an external voltage. When an internal voltage generated by an internal circuit of the electronic device is greater than the reduced voltage, the first node outputs the internal voltage as a first voltage. When the internal voltage is less than the reduced voltage, the first node outputs the reduced voltage as the first voltage. The first transistor is coupled with the signal pad and the first node. The second transistor is coupled with a second terminal of the first transistor and a fixed-voltage terminal. The control logic operates according to the first voltage to control switching operations of the second transistor.