High-Voltage Latch Leakage Current Control
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Solution Overview
Problem
High-voltage latches in non-volatile memory chips experience excessive leakage currents due to leaky NMOS transistors, which can reduce the high voltage required for proper data writing, leading to malfunctioning memory write functions.
Innovation Solution
A switching circuit is introduced between the high-voltage terminal and ground, providing low impedance during data loading and high impedance during high-voltage write mode to limit leakage current, using NMOS switching transistors that are minimally turned on by a low bias voltage to maintain high impedance and reduce current flow through low-threshold NMOS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If low-threshold NMOS transistors are used in high-voltage latch circuits, then the latch can operate with low VDD voltage, but excessive leakage current occurs at high write voltages
Solution Approach 1:
A switching transistor is introduced as an intermediary component between the low-threshold NMOS transistor and ground. This switching transistor acts as a mediator that blocks the leakage current path during high-voltage write operations while allowing the low-threshold NMOS transistor to function normally during low-voltage operation modes.
Solution Approach 2:
The impedance of the switching circuit is dynamically changed based on the operating mode. During high-voltage write operations, the switching transistor is turned off to present high impedance and block leakage current. During low-voltage operation, the switching transistor is turned on to present low impedance and allow normal signal flow.
2Quantity of substance
If multiple high-voltage latch circuits are used in parallel, then data storage capacity increases, but total leakage current increases and loads down the high-voltage generator
Solution Approach 1:
The solution segments the leakage current path for each latch circuit by introducing individual switching transistors. This allows each latch to independently control its own leakage current, preventing the cumulative effect from loading down the high-voltage generator while maintaining the ability to have multiple latch circuits in parallel.
3Productivity
If high voltage is applied to the latch during write mode, then data can be written into memory cells, but leakage current causes voltage drop below required level
Solution Approach 1:
The switching transistor converts the harmful leakage current into a controllable parameter. By strategically placing the switching transistor and controlling its state, the design transforms the potential voltage drop problem into a controlled impedance switching mechanism that actually protects the high-voltage level stability during write operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively limits leakage current during high-voltage write operations, ensuring that the high voltage is maintained across the latch circuits, preventing voltage drops and ensuring proper data writing into non-volatile memory cells.
Implementation Method 1
providing low impedance during data loading and high impedance during high-voltage write mode to limit leakage current
Implementation Method 2
using NMOS switching transistors that are minimally turned on by a low bias voltage to maintain high impedance and reduce current flow
Data Source
AI summary
An improved cross-coupled CMOS high-voltage latch that is used for storing data bits to be written to memory cells of a non-volatile memory is provided with a switching circuit that, during writing of data bits into the memory cells of the latch, provides a high series impedance between one leg of the latch and ground to limit leakage current. A large number of latches are connected in parallel and their accumulated leakage currents are limited by the switching circuit to prevent overload of a high-voltage generator, such as a charge pump circuit, for the high-voltage latch, so that data can be properly written in the memory cells of the non-volatile memory.