High-Voltage LDMOS Isolation Structure for Low Gate-Drain Capacitance
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Solution Overview
Problem
As semiconductor devices are scaled down, maintaining low gate-to-drain capacitance and high breakdown voltage becomes challenging for high power applications, particularly in radio frequency power amplifiers, where existing technologies struggle to balance conduction resistance and high-frequency operation.
Innovation Solution
The method involves forming a laterally diffused metal-oxide-semiconductor (LDMOS) transistor with a shallow trench isolation structure and conductive field plates, which reduces the equivalent length of the conduction path and maintains high breakdown voltage while lowering capacitance between the gate and drain, enabling operation at high frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are scaled down to maintain integration density, then integration density is improved, but breakdown voltage and gate-to-drain capacitance performance deteriorate
Solution Approach 1:
The patent transitions from planar device scaling to vertical channel architecture, stacking multiple transistor layers vertically to achieve high integration density while maintaining each transistor's breakdown voltage performance through controlled channel length and electric field distribution in the vertical dimension
Solution Approach 2:
The patent applies different doping concentrations and material compositions to specific regions (channel, source, drain, isolation areas) to locally optimize electric field distribution, enabling high breakdown voltage at critical interfaces while maintaining overall device scalability for high integration density
2Productivity
If semiconductor devices are scaled down, then integration density is improved, but gate-to-drain capacitance increases
Solution Approach 1:
The vertical channel architecture separates gate and drain regions in the vertical dimension, reducing lateral overlap and thereby decreasing gate-to-drain capacitance while enabling higher integration density through multi-layer stacking
Solution Approach 2:
The patent introduces carefully engineered isolation structures and dielectric layers as intermediaries between gate and drain regions, providing electric field shielding and reducing capacitive coupling while maintaining device scalability
3Productivity
If conventional scaling is used to increase integration density, then productivity is improved, but conduction resistance increases
Solution Approach 1:
The vertical channel structure provides additional conduction pathways in the vertical dimension, reducing lateral current density and conduction resistance while achieving high integration density through multi-layer stacking
Solution Approach 2:
The patent merges source and drain regions with extended lateral overlap under the gate, creating low-resistance contact areas and optimizing carrier injection while maintaining scaled device dimensions for high integration density
Data Source
AI summary
A semiconductor device includes a first well of a first conductivity type near a surface of a semiconductor substrate, and a second well of a second conductivity type near the surface of the semiconductor substrate. The semiconductor device includes a transistor comprising: (i) a first source/drain region formed in the first well; (ii) a second source/drain region formed in the second well; and (iii) a gate structure formed near the surface of the semiconductor substrate and separated from the second source/drain region at least with a portion of a third well of the second conductive type. The semiconductor device includes an isolation structure formed near the surface of the semiconductor substrate and further separating the second source/drain region from the gate structure. The semiconductor device includes a plurality of field plates formed above at least one of the portion of the third well or the isolation structure.