High-Voltage Memory Programming with Bit-Line-Controlled Second Word Lines

Solution Overview

Problem

Existing memory cell programming methods incur high active power consumption due to asserting all second word lines in parallel with word lines, leading to increased capacitive loading and power usage.

Innovation Solution

Coupling second word lines in parallel with bit lines instead of word lines, using low threshold voltage devices, and incorporating second bit lines in parallel with word lines to reduce capacitive loading and active power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If all second word lines are asserted in parallel with word lines during programming, then unselected stacked access transistors are protected, but active power consumption and capacitive loading increase significantly

Engineering Contradiction:

Improveprotection of unselected stacked access transistorsVSAvoidactive power consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent segments the control of second word lines by coupling them in parallel with bit lines instead of word lines. This segmentation allows selective activation of second word lines corresponding only to unselected memory cells during programming, rather than asserting all second word lines simultaneously. The result is reduced capacitive loading and active power consumption while maintaining protection of unselected stacked access transistors.

Inventive Principle:

Principle #1Segmentation

2Reliability

If all second word lines are asserted in parallel with word lines during programming, then unselected stacked access transistors are protected, but capacitive loading increases significantly

Engineering Contradiction:

Improveprotection of unselected stacked access transistorsVSAvoidcapacitive loading

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the control of second word lines by coupling them in parallel with bit lines instead of word lines. This segmentation allows selective activation of second word lines corresponding only to unselected memory cells during programming, rather than asserting all second word lines simultaneously. The result is reduced capacitive loading and active power consumption while maintaining protection of unselected stacked access transistors.

Inventive Principle:

Principle #1Segmentation

3Device complexity

If second word lines are coupled in parallel with word lines, then protection is simplified, but power consumption increases by up to 256 times

Engineering Contradiction:

Improveprotection mechanism simplicityVSAvoidactive power consumption

Core Design Contradiction:

Device complexityVSUse of energy by moving object

Solution Approach 1:

The patent introduces bit lines as intermediary control lines for the second word lines. Instead of directly coupling second word lines to word lines, the bit lines serve as mediators that enable selective activation of second word lines during programming operations. This intermediary approach reduces power consumption by up to 256 times compared to direct parallel coupling, while still providing necessary protection of unselected stacked access transistors.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS12412620B2Second word line combined with y-mux signal in high voltage memory program

Publication Date: 2025.09.09 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A memory device is disclosed. The memory device includes a plurality of memory cells arranged in a plurality of rows and a plurality of columns; a plurality of word lines, each of the word lines coupled to a corresponding row of the memory cells; a plurality of bit lines, each of the bit lines coupled to a corresponding column of the memory cells; and a plurality of second word lines, each of the second word lines coupled to a corresponding column of the memory cells.