High-Voltage MOS Structure With RPO Silicide Blocking
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Solution Overview
Problem
The integration of high voltage devices with low voltage devices in system-on-chip (SoC) technology poses challenges due to the complexity of processing and manufacturing semiconductor integrated circuits (ICs).
Innovation Solution
The proposed solution involves the fabrication of a high voltage semiconductor device with a configuration that includes an n-type high voltage MOS (NHVMOS) device, where the isolation feature structure between the pickup region and the source region is eliminated, and a resist protective oxide (RPO) layer is used to block the silicide process, thereby reducing substrate current and preventing parasitic bipolar junction transistor (BJT) triggering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If high voltage devices are integrated with low voltage devices in SoC technology, then system functionality is enhanced, but processing and manufacturing complexity increases
Solution Approach 1:
The patent segments the semiconductor device into distinct high voltage and low voltage regions with separate well structures (first well for high voltage, second well for low voltage). This segmentation allows each region to be optimized independently for its specific voltage requirements while maintaining a unified device architecture, thereby enabling enhanced system functionality without proportionally increasing processing and manufacturing complexity.
2Reliability
If isolation feature structure is used between pickup region and source region, then parasitic BJT triggering is prevented, but substrate current increases
Solution Approach 1:
The patent extracts or removes the isolation feature structure that traditionally separates the pickup region and source region. By eliminating this isolation structure, the patent reduces substrate current while maintaining parasitic BJT prevention through alternative means (the specific well structure configuration and doping profiles), thereby resolving the contradiction between reliability and energy loss.
3Loss of energy
If resist protective oxide layer is used to block silicide process, then substrate current is reduced, but fabrication steps increase
Solution Approach 1:
The patent applies the resist protective oxide layer in advance during the fabrication process to prevent silicide formation in specific regions. This preliminary protective action reduces substrate current by blocking unwanted silicide reactions, and the process is integrated into the existing fabrication flow, thereby achieving energy reduction while managing fabrication complexity through process integration.
4Reliability
If breakdown voltage is enhanced, then device reliability is improved, but conductive resistance may increase
Solution Approach 1:
The patent implements local quality variations through different well structures and doping profiles in specific regions of the device. The first well and second well are configured with different properties optimized for high voltage and low voltage operations respectively. This local optimization allows the device to achieve high breakdown voltage in critical regions while maintaining low conductive resistance in current-carrying paths, thereby resolving the contradiction between reliability and energy loss.
Data Source
AI summary
A semiconductor structure is disclosed. The semiconductor structure includes: a substrate of a first conductivity; a first region of the first conductivity formed in the substrate; a second region of the first conductivity formed in the first region, wherein the second region has a higher doping density than the first region; a source region of a second conductivity formed in the second region; a drain region of the second conductivity formed in the substrate; a pickup region of the first conductivity formed in the second region and adjacent to the source region; and a resist protective oxide (RPO) layer formed on a top surface of the second region. An associated fabricating method is also disclosed.