High Voltage Semiconductor Device Level Shift Circuit Integration
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Solution Overview
Problem
High voltage semiconductor devices with level shift circuits face challenges in reducing chip area, suppressing circuit malfunctions and transmission delay times, and managing power loss and dV/dt surges during switching, which affect switching response speed.
Innovation Solution
A high voltage semiconductor device is designed with a second conductivity type semiconductor region on a first conductivity type substrate, featuring a logic circuit, insulated gate field effect transistors with specific source and drain regions, and a load resistance formed between the drain and pick-up regions, optimized to reduce parasitic capacitance and resistance variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a general level shift circuit is incorporated in a high voltage IC, then the circuit can drive high side gate drivers, but the chip area increases and transmission delay time increases
Solution Approach 1:
The patent merges the level shift function with the existing high voltage MOSFET structure by utilizing the drain region as both the MOSFET drain and the level shift circuit input node. This integration eliminates separate level shift circuit components and reduces chip area while maintaining drive capability.
Solution Approach 2:
The high voltage MOSFET drain region serves multiple functions: it acts as the drain terminal for the MOSFET itself, the input node for the level shift circuit, and provides the voltage sensing function for level shifting. This multi-functionality reduces the number of dedicated components needed.
2Ease of operation
If a general level shift circuit is incorporated in a high voltage IC, then the circuit can drive high side gate drivers, but the transmission delay time increases
Solution Approach 1:
By combining the level shift function with the MOSFET drain structure, the patent eliminates intermediate signal transmission stages. The voltage change at the MOSFET drain directly controls the level shift output, reducing the number of switching transitions and associated delays.
Solution Approach 2:
The patent skips the traditional multi-stage level shift process by directly utilizing the MOSFET drain voltage to control the level shift output. This direct coupling rushes through the level shifting process in a single stage, reducing overall transmission delay.
3Ease of manufacture
If conventional level shift circuit structures are used, then the circuit design is straightforward, but parasitic capacitance increases causing circuit malfunctions and power loss
Solution Approach 1:
The patent merges the level shift input node with the MOSFET drain region, eliminating separate connecting structures that would introduce parasitic capacitance. This integration removes unnecessary interfaces between components.
Solution Approach 2:
The patent extracts and eliminates the parasitic capacitance sources by removing separate level shift circuit components and their associated interconnections. Only the essential MOSFET structure remains, minimizing parasitic effects.
Data Source
AI summary
An n well region and an n−region surrounding the n well region are provided in the surface layer of a p−silicon substrate. The n−region includes breakdown voltage regions in which high voltage MOSFETs are disposed. The n well region includes a logic circuit region in which a logic circuit is disposed. A p− opening portion is provided between a drain region of each high voltage MOSFET and the logic circuit region. An n buffer region used as load resistances is provided between a second pick-up region and the drain region. The p−opening portion is provided between the n buffer region and logic circuit region. By so doing, it is possible to realize a reduction in the area of chips, and provide a high voltage semiconductor device having a level shift circuit with a high switching response speed.