High-Voltage Nanosheet Transistor Integration on a Common Substrate
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Solution Overview
Problem
Current methods for fabricating nano-sheet field effect transistors (FETs) for high-voltage applications, such as one-time programmable (OTP) memory cells, face challenges in achieving efficient operation at high voltages while maintaining low power consumption and manufacturing cost-effectiveness.
Innovation Solution
The simultaneous fabrication of high-voltage nano-sheet FETs (HV-NS FETs) and low-voltage gate-all-around FETs (LV-GAA FETs) on a common substrate, utilizing a gate dielectric stack with a silicon oxide layer and high-k dielectric, and alternating Si and SiGe nano-sheet layers, allows for operation at 5 Volts with reduced power consumption and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional fabrication methods are used for high-voltage nano-sheet FETs, then device operation at high voltage is achieved, but power consumption increases and manufacturing cost rises
Solution Approach 1:
The patent combines the fabrication processes for high-voltage nano-sheet FETs and low-voltage gate-all-around FETs into a single integrated process flow. This merging allows both device types to be manufactured simultaneously on the same substrate using shared process steps, thereby reducing overall manufacturing cost and power consumption while maintaining high-voltage operation capability
Solution Approach 2:
The fabrication process is designed to be universal, accommodating both high-voltage and low-voltage device architectures through the same sequence of steps. The process can selectively form different device types in different regions of the substrate, enabling multi-functionality and reducing the need for separate manufacturing lines
2Reliability
If separate fabrication processes are used for high-voltage and low-voltage FETs, then device performance is optimized, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges previously separate fabrication processes into a single integrated process. The combined process uses the same sequence of steps—forming sacrificial layers, depositing gate dielectrics, creating gate electrodes, and removing sacrificial materials—to manufacture both high-voltage nano-sheet FETs and low-voltage gate-all-around FETs, thereby reducing manufacturing complexity while maintaining device performance
Solution Approach 2:
The unified fabrication process incorporates local quality variations through selective masking and patterning steps. Different regions of the substrate can be configured to form different device types (high-voltage or low-voltage) based on local process conditions, allowing performance optimization for each device type while using the same overall process
3Power
If high-voltage FETs are fabricated using traditional methods, then high voltage operation is achieved, but manufacturing cost-effectiveness decreases
Solution Approach 1:
The patent combines the fabrication of high-voltage and low-voltage FETs into a single manufacturing run, allowing both device types to be produced simultaneously on the same substrate. This merging eliminates the need for separate manufacturing lines, reduces equipment utilization costs, and improves overall cost-effectiveness while maintaining high-voltage operation capability
Solution Approach 2:
The fabrication process uses parameter changes in the sacrificial layer removal step to selectively form different device types. By adjusting etch conditions and masking patterns, the process can produce high-voltage nano-sheet FETs with appropriate channel thickness and gate control, optimizing manufacturing cost-effectiveness for high-voltage applications
Data Source
AI summary
The present disclosure is directed to methods for the formation of high-voltage nano-sheet transistors and low-voltage gate-all-around transistors on a common substrate. The method includes forming a fin structure with first and second nano-sheet layers on the substrate. The method also includes forming a gate structure having a first dielectric and a first gate electrode on the fin structure and removing portions of the fin structure not covered by the gate structure. The method further includes partially etching exposed surfaces of the first nano-sheet layers to form recessed portions of the first nano-sheet layers in the fin structure and forming a spacer structure on the recessed portions. In addition, the method includes replacing the first gate electrode with a second dielectric and a second gate electrode, and forming an epitaxial structure abutting the fin structure.