High Voltage Tolerant Output Circuit for CEC Protocol
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Solution Overview
Problem
Control chips supporting the Consumer Electronics Control (CEC) protocol face challenges in voltage endurance, as the voltage required for the CEC protocol (e.g., 3.3 V) exceeds the voltage endurance of internal components, which can lead to excessive voltage differences and potential damage.
Innovation Solution
A high voltage tolerant output circuit is designed, comprising a boost circuit, a first bias circuit, and a buffer circuit, where the boost circuit includes a transistor and an output node, the bias circuit divides the output voltage to set the control terminal voltage, and the buffer circuit sets the second terminal voltage based on an input voltage, ensuring the output voltage is positively correlated and within safe limits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If advanced process is applied to reduce circuit area and save power, then circuit area and power consumption are reduced, but voltage endurance of internal components becomes lower than output voltage requirement
Solution Approach 1:
A voltage division circuit is introduced as an intermediary between the output node and the control terminal of the first transistor. This circuit divides the output voltage to provide a reduced voltage to the control terminal, ensuring that the voltage difference across internal components remains within safe limits while allowing the output to reach the required 3.3V CEC protocol level
Solution Approach 2:
The voltage division circuit dynamically adjusts the voltage parameter at the control terminal based on the output voltage. By changing the voltage parameter through division, the circuit ensures that internal components experience reduced voltage stress while the output maintains the required high voltage level for CEC protocol operation
2Power
If output voltage is increased to meet CEC protocol specification, then CEC protocol compliance is achieved, but internal components experience excessive voltage difference
Solution Approach 1:
The voltage division circuit serves as a protective intermediary that decouples the high output voltage requirement from the low voltage endurance of internal components. It allows the output node to reach 3.3V for CEC compliance while presenting a reduced voltage to the control terminal, preventing excessive voltage differences
Solution Approach 2:
Different parts of the circuit are assigned different voltage characteristics: the output node operates at high voltage (3.3V) to meet CEC protocol requirements, while the control terminal operates at reduced voltage to protect internal components. This local differentiation of voltage quality resolves the contradiction between output power and voltage stress
Data Source
AI summary
A high voltage tolerant output circuit includes a boost circuit, a first bias circuit, and a buffer circuit. The boost circuit includes a first transistor and an output node. A first terminal of the first transistor is coupled with the output node. The first bias circuit is coupled with the output node and a control terminal of the first transistor, and for dividing the output voltage of the output node. The first bias circuit is further configured to transmit the divided output voltage to the control terminal of the first transistor. The buffer circuit is coupled with a second terminal of the first transistor, and for setting a first voltage of the second terminal of the first transistor. The output voltage is positive correlated to the first voltage, and a maximum value of the output voltage is higher than or equal to a maximum value of the first voltage.