High-Voltage Transistor Package With Dielectric Substrate Isolation
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Solution Overview
Problem
High voltage semiconductor chip packaging faces challenges such as sensitivity of the high-voltage edge, requiring a large distance from low-voltage terminal elements for field line exit, and issues with heat dissipation and manufacturing costs.
Innovation Solution
A semiconductor package design incorporating a dielectric inorganic substrate with metal structures that connects to both low and high voltage electrodes, providing a spacer and adaptor function, allowing for flexible terminal geometries and improved heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large distance is maintained between the chip edge and low-voltage terminal elements, then the high-voltage edge sensitivity is reduced and field line exit is improved, but the package area increases and device complexity increases
Solution Approach 1:
The patent introduces a third dimension by bonding the chip to the underside of the substrate, allowing terminal elements to be positioned on the opposite side of the chip edge. This vertical separation in the Z-dimension eliminates the need for large lateral distances, maintaining high-voltage edge sensitivity while minimizing package area.
Solution Approach 2:
The substrate acts as an intermediary between the chip and the terminal elements. By positioning terminal elements on the substrate rather than directly on the chip, the patent creates spatial separation that protects the high-voltage edge while maintaining compact dimensions. The substrate mediates the electrical connection while providing physical isolation.
2Ease of manufacture
If conventional packaging methods are used with direct chip mounting, then manufacturing is simpler, but heat dissipation performance is insufficient and electrical performance deteriorates due to capacitive losses and electromagnetic interference
Solution Approach 1:
The substrate serves as an intermediary thermal management component between the chip and the heat sink. This intermediary structure provides dedicated thermal pathways through thermal vias and conductive layers, improving heat dissipation performance while maintaining manufacturing feasibility through standardized substrate processing.
Solution Approach 2:
The patent segments the thermal management function by creating separate thermal pathways through the substrate, distinct from electrical signal pathways. This segmentation allows optimized thermal conduction through dedicated thermal vias and ground planes, improving heat dissipation without complicating the overall manufacturing process.
3Area of stationary object
If terminal elements are positioned close to the chip edge for compact packaging, then package area is reduced, but the high-voltage edge becomes sensitive and electrical performance deteriorates
Solution Approach 1:
The patent resolves the conflict between compact packaging and electrical performance by moving terminal elements to the underside of the chip in a different dimensional plane. This vertical repositioning allows compact top-view packaging while maintaining electrical isolation through the substrate thickness, eliminating electromagnetic interference and capacitive losses.
4Reliability
If a thick substrate is used to provide adequate spacing for field line exit, then high-voltage edge sensitivity is improved, but the substrate occupies more volume and increases device complexity
Solution Approach 1:
The patent utilizes the vertical dimension (Z-axis) through thick substrate bonding to achieve field line exit performance. By bonding the chip to the underside of a substrate of adequate thickness, the patent creates sufficient spacing for field line termination without requiring large lateral dimensions, thus minimizing overall device volume while maintaining reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances electrical and thermal performance, reduces manufacturing complexity, and improves reliability by allowing direct bonding to terminal structures without capacitive losses and electromagnetic interference.
Implementation Method 1
a dielectric inorganic substrate comprising a pattern of first metal structures running through the dielectric inorganic substrate
Implementation Method 2
The front side of the semiconductor transistor chip is attached to the dielectric inorganic substrate by a wafer bond connection
Data Source
AI summary
A high voltage semiconductor package includes a semiconductor device. The semiconductor device includes a high voltage semiconductor transistor chip having a front side and a backside. A low voltage load electrode and a control electrode are disposed on the front side of the semiconductor transistor chip. A high voltage load electrode is disposed on the backside of the semiconductor transistor chip. The semiconductor package further includes a dielectric inorganic substrate. The dielectric inorganic substrate includes a pattern of first metal structures running through the dielectric inorganic substrate and connected to the low voltage load electrode, and at least one second metal structure running through the dielectric inorganic substrate and connected to the control electrode. The front side of the semiconductor transistor chip is attached to the dielectric inorganic substrate by a wafer bond connection, and the dielectric inorganic substrate has a thickness of at least 50 μm.