High-Voltage Pin Placement for Creepage Compliance
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Solution Overview
Problem
High-voltage electronic devices require sophisticated power supplies that deliver stable, clean power with high efficiency, but existing packaging solutions struggle to meet safety standards for creepage and clearance distances, especially in high-density designs, leading to potential arc discharge risks.
Innovation Solution
The proposed solution involves arranging high-voltage pins at the center of the package, away from the edges, to ensure creepage distance is met within the package itself, allowing for a safer, more robust, and compact high-voltage package design that complies with safety standards like IEC 61010-1, using a system package with low-voltage and high-voltage pins, and incorporating ground pins to isolate IO pins from high-voltage pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If high-voltage pins are placed at the edges of the package, then board area utilization is improved, but safety standards for creepage and clearance distances cannot be met, increasing arc discharge risk
Solution Approach 1:
The patent inverts the conventional pin placement approach by positioning high-voltage pins at the center of the package rather than at the edges. This inversion allows the creepage and clearance distances to be measured from the center outward, enabling compliance with safety standards while maintaining compact board area utilization. The ground pins are placed between the high-voltage pins and package edges to create proper isolation barriers.
Solution Approach 2:
The patent introduces ground pins as intermediary elements positioned between the high-voltage pins and the package edges. These ground pins act as mediators that create the necessary creepage and clearance distances, providing electrical isolation and preventing arc discharge while allowing the high-voltage pins to be centrally located for compact design.
2Reliability
If creepage and clearance distances are increased to meet safety standards, then arc discharge risk is reduced, but package size and board area increase
Solution Approach 1:
The patent resolves this contradiction by inverting the traditional approach: instead of placing high-voltage pins at edges and extending outward for clearance, the pins are placed at the center and clearance is achieved by extending ground isolation outward to the edges. This allows maximum creepage and clearance distances within the minimum package area.
Solution Approach 2:
The patent merges the high-voltage pin placement with the package center location, and combines the ground isolation structure with the package boundary. This integration allows the creepage and clearance distances to be efficiently utilized within the package footprint without requiring additional board area.
3Reliability
If high-voltage pins are isolated from edges with ground pins, then safety and reliability are improved, but device complexity increases
Solution Approach 1:
The patent segments the package into distinct functional zones: a central high-voltage region, intermediate ground isolation regions, and outer low-voltage regions. This segmentation provides clear electrical isolation while maintaining an organized, systematic pin arrangement that is manageable in complexity.
Solution Approach 2:
The patent employs asymmetric pin placement where high-voltage pins are positioned at the center while ground pins are strategically distributed toward the edges. This asymmetric arrangement optimizes isolation effectiveness while maintaining reasonable structural simplicity compared to symmetric designs that would require larger dimensions.
Data Source
AI summary
Techniques, methods, and systems are provided for packaging high-voltage packages. On example system package includes circuitries comprising circuit elements; and a plurality of connection pins including low-voltage pins; input/output (IO) pins arranged in regions proximate edges of the system package; and high-voltage pins arranged in an inner region of the system package away from all edges of the system package.