High Voltage Reset Driver and Isolated Memory Array in DMDs
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Solution Overview
Problem
The integration of bipolar reset drivers and associated circuitry onto a CMOS substrate in digital micromirror devices (DMDs) is challenging due to the large negative reset voltage, which can forward bias PN junctions and increase processing costs.
Innovation Solution
A high voltage reset driver and isolated memory array are integrated on a semiconductor substrate, with the memory array isolated from the grounded substrate using a buried layer, and the operating voltages of the memory array are shifted with respect to the reset voltage, allowing the reset driver to drive the reset voltage effectively without damaging the memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If bipolar reset drivers are integrated onto CMOS substrate, then reset functionality is achieved, but the large negative reset voltage forward biases PN junctions and increases processing costs
Solution Approach 1:
The device is segmented into two distinct regions: a first region containing the memory array operating at standard CMOS voltages, and a second region containing the reset driver operating at high voltage. This spatial segmentation allows each region to be optimized independently, enabling reset functionality without exposing the entire CMOS substrate to high voltage stress that would forward bias PN junctions.
Solution Approach 2:
A buried layer acts as an intermediary structure between the standard CMOS substrate and the high voltage reset driver. This buried layer isolates the high voltage operations from the standard CMOS circuitry, preventing the large negative reset voltage from forward biasing PN junctions in the memory array while still enabling reset functionality in the isolated second region.
2Ease of manufacture
If high voltage reset is integrated with CMOS process, then low cost integration is achieved, but the structure must withstand higher breakdown voltages
Solution Approach 1:
The segmentation into isolated high voltage and standard voltage regions allows the high voltage reset driver to be designed with appropriate breakdown voltage tolerance in its specific region, without requiring the entire CMOS substrate to withstand high voltages. This localized approach maintains low integration costs while ensuring sufficient strength where needed.
Solution Approach 2:
Different regions of the device are given different quality characteristics: the first region maintains standard CMOS properties optimized for low-voltage memory operation, while the second region is specifically engineered with high voltage tolerance for reset operations. This local differentiation achieves the necessary breakdown voltage strength only where required, minimizing overall processing complexity and cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables low-cost integration of high voltage reset functionality within a CMOS process, resulting in a more robust structure with higher breakdown voltages and avoiding the forward biasing of PN junctions.
Implementation Method 1
The memory array is isolated from the grounded substrate with a buried layer
Implementation Method 2
producing, using the set of shifted voltages, an electrostatic field between at least one micromirror and at least one address electrode
Data Source
AI summary
A method of operating a semiconductor device, a semiconductor device and a digital micromirror system are presented. In an embodiment, the semiconductor device comprises a grounded substrate, a memory array, and a reset driver. The memory array may be isolated from the grounded substrate with a buried layer. The set of voltages of the memory array may be shifted with respect to a reset voltage. The reset driver may drive the reset voltage and the reset driver may have at least one extended drain transistor in the grounded substrate.