High-Voltage Schmitt Trigger Using BOXFETs to Avoid SOA Limits

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Solution Overview

Problem

Schmitt triggers in fully depleted semiconductor-on-insulator processing technology platforms face challenges with low safe operating area (SOA) limitations, making them impractical for high voltage input buffers, and require additional circuitry to accommodate high input voltages, increasing complexity and area.

Innovation Solution

A configurable inverting Schmitt trigger design using a combination of buried oxide field effect transistors (BOXFETs) and laterally diffused metal oxide semiconductor field effect transistors (LDMOSFETs) with adjustable reference voltages to manage SOA violations and tune hysteresis levels, allowing operation in high voltage environments without additional circuitry.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If LDMOSFETs are used in Schmitt triggers for reduced area consumption, then area is reduced, but safe operating area (SOA) is limited making them impractical for high voltage inputs

Engineering Contradiction:
Improvecircuit areaVSAvoidsafe operating area
Core Design Contradiction:
Area of moving objectVSReliability

Solution Approach 1:

The patent applies local quality by using different transistor types in different regions of the circuit: BOXFETs are used specifically for the input stage where high voltage tolerance is required, while LDMOSFETs are used for other stages where area efficiency is more important. This localized application of different device characteristics resolves the contradiction between area efficiency and voltage tolerance.

Inventive Principle:
Principle #3Local quality

2Adaptability or versatility

If additional circuitry is added to accommodate high input voltages, then high voltage capability is achieved, but circuit complexity increases

Engineering Contradiction:
Improvehigh voltage capabilityVSAvoidcircuit complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent changes the voltage rating parameter of the transistors by selecting BOXFETs with higher voltage ratings for the input stage. This parameter change allows the circuit to handle high input voltages (up to 5.0V or beyond) without requiring additional protective circuitry, thus achieving high voltage capability while maintaining simple circuit architecture.

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If additional circuitry is added to accommodate high input voltages, then high voltage capability is achieved, but circuit area increases

Engineering Contradiction:
Improvehigh voltage capabilityVSAvoidcircuit area
Core Design Contradiction:
Adaptability or versatilityVSArea of moving object

Solution Approach 1:

The patent uses BOXFETs specifically in the input stage where high voltage tolerance is needed, while using smaller LDMOSFETs in other stages. This localized approach provides high voltage capability where required without increasing the overall circuit area, as the high-voltage transistors are only used where necessary rather than throughout the entire circuit.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12451875B2High-voltage Schmitt trigger
Publication Date: 2025.10.21 GLOBALFOUNDRIES US INC
  • US12451875B2 patent drawing
  • US12451875B2 patent drawing
  • US12451875B2 patent drawing

AI summary

In a disclosed Schmitt trigger, an input stage includes a first p-channel field effect transistor (PFET) and a second PFET, which are connected in series to a VDD rail, and a first n-channel field effect transistor (NFET) and a second NFET, which are connected in series between ground and the second PFET. An output stage includes additional FETs for hysteresis. The first PFET and first NFET are different from the other FETs and have a higher voltage rating. For example, the first PFET and first NFET can be buried oxide field effect transistors (BOXFETs) and the other FETs can be laterally diffused metal oxide semiconductor field effect transistors (LDMOSFETs)). Gates of the first PFET and first NFET are connected to an input node. Gates of the second PFET and NFET are connected to receive reference voltages to prevent safe operating area (SOA) violations and control trigger voltage levels.