High Voltage Semiconductor Device Halo Implant
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Solution Overview
Problem
Traditional high voltage semiconductor devices, such as LDMOS transistors, face challenges with increased on resistance and device size due to the source-drain punch-through effect, and p-type diffused metal oxide semiconductor transistors have higher on resistance compared to n-type due to lower hole carrier mobility.
Innovation Solution
The implementation of a high voltage semiconductor device structure that includes a halo or pocket implant region to mitigate the punch-through effect, reducing on resistance and device size by shrinking the transistor channel, achieved through the use of a lightly doped region with specific conductivity types and doping concentrations, and the formation of epitaxial layers with opposing conductivity types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the channel length is extended to prevent source-drain punch-through effect, then the punch-through effect is mitigated, but the device size and on resistance increase
Solution Approach 1:
The patent introduces a lightly doped region with specific conductivity type adjacent to the source doped region, creating a localized doping structure that prevents punch-through effect in a specific area without requiring overall channel length extension. This local modification maintains device compactness while achieving punch-through prevention.
Solution Approach 2:
The patent modifies the doping concentration and conductivity type parameters by introducing a lightly doped region with first conductivity type near the source, rather than uniformly increasing channel length. This parameter change approach prevents punch-through while maintaining shorter channel dimensions and lower on resistance.
2Reliability
If the channel length is extended to prevent source-drain punch-through effect, then the punch-through effect is mitigated, but the on resistance increases
Solution Approach 1:
The lightly doped region is positioned specifically adjacent to the source doped region to create a localized barrier against carrier punch-through. This localized approach prevents the need for overall channel length extension, thereby maintaining lower on resistance while still achieving punch-through prevention.
Solution Approach 2:
By changing the doping parameters (introducing lightly doped region with first conductivity type) in a specific location rather than extending channel length, the patent achieves punch-through prevention with minimal impact on on resistance, improving overall device performance.
3Ease of manufacture
If p-type diffused metal oxide semiconductor is used, then the device structure is formed, but the on resistance is higher due to lower hole carrier mobility
Solution Approach 1:
The patent introduces a lightly doped region with first conductivity type (opposite to the p-type substrate) adjacent to the source region. This localized n-type (or p-type opposite to substrate) region creates a beneficial electric field distribution that enhances carrier transport, reducing on resistance while maintaining the p-type device structure.
Solution Approach 2:
The patent creates a composite doping structure by combining the p-type substrate, p-type high voltage well, and lightly doped region with first conductivity type (opposite conductivity). This composite structure leverages the advantages of both conductivity types to reduce on resistance while maintaining manufacturability of the p-type device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces on resistance and device size by minimizing leakage current and channel length, improving the performance of high voltage semiconductor devices.
Implementation Method 1
A lightly doped region with a first conductivity type is between the source and drain doped regions and relatively near to the source doped region
Implementation Method 2
the mobility of a hole carrier is lower than that of the electron carrier
Implementation Method 3
LDMOS transistors typically control current flowing between a drain and a source by a channel resulting from the gate voltage
Implementation Method 4
An epitaxial layer with a first conductivity type is formed on a semiconductor substrate
Data Source
AI summary
A high voltage semiconductor device is provided. The device includes a semiconductor substrate having a high voltage well with a first conductivity type therein. A gate structure is disposed on the semiconductor substrate of the high voltage well. A source doped region and a drain doped region are in the high voltage well on both sides of the gate structure, respectively. A lightly doped region with the first conductivity type is between the source and drain doped regions and relatively near to the source doped region. The disclosure also presents a method for fabricating a high voltage semiconductor device.