High Voltage Semiconductor Device With Nested Deep Wells
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Solution Overview
Problem
Conventional high voltage semiconductor devices, such as LDMOS transistor devices, face challenges in enhancing electrical performance, voltage endurance, and reliability, particularly in high voltage applications, due to limitations in their structural design and manufacturing processes.
Innovation Solution
The introduction of deep well regions with complementary conductivity types, where the second deep well region is located above the first deep well region, and the first well region is connected to the first deep well region, with the gate structure positioned on the semiconductor substrate, enhancing electrical performance by improving breakdown voltage and reducing on-state resistance without increasing device area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deep well regions with complementary conductivity types are introduced, then breakdown voltage is enhanced and on-state resistance is reduced, but device structure becomes more complex
Solution Approach 1:
The patent implements nested well structures where first deep well regions and second deep well regions are positioned at different depths within the drift region. The first deep well regions extend from a first depth to a second depth, while the second deep well regions extend from a third depth to a fourth depth, creating a vertically stacked, nested configuration that enhances breakdown voltage without significantly increasing lateral device area.
Solution Approach 2:
The patent transitions from conventional lateral well structures to a three-dimensional vertical arrangement by positioning deep well regions at multiple depth levels within the drift region. This vertical dimensionality allows for enhanced electrical performance through improved field distribution and carrier control, while maintaining compact lateral footprint.
2Reliability
If deep well regions with complementary conductivity types are introduced, then on-state resistance is reduced, but manufacturing process becomes more complex
Solution Approach 1:
The patent employs preliminary doping actions during the manufacturing process, where the first deep well regions and second deep well regions are formed with predetermined conductivity types and depth profiles before final device assembly. This preliminary structuring simplifies subsequent processing steps and ensures optimal electrical characteristics are achieved during fabrication.
3Reliability
If multiple deep well regions are positioned at different depths, then electrical performance is improved, but device area increases
Solution Approach 1:
The patent utilizes vertical nesting of deep well regions where first deep well regions and second deep well regions are stacked at different depth levels within the drift region. This nested configuration provides enhanced electrical performance through improved field distribution and carrier control while maintaining a compact lateral footprint, as the structures are arranged vertically rather than laterally.
Data Source
AI summary
A high voltage semiconductor device includes a semiconductor substrate, first and second deep well regions, and first and second well regions disposed in the semiconductor substrate. The second deep well region is located above the first deep well region. The first well region is located above the first deep well region. The second well region is located above the second deep well region. A conductivity type of the second deep well region is complementary to that of the first deep well region. A conductivity type of the second well region is complementary to that of the first well region and the second deep well region. A length of the second deep well region is greater than or equal to that of the second well region and less than that of the first deep well region. The first well region is connected with the first deep well region.