High Voltage Semiconductor Device With Segmented Isolation Regions

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Solution Overview

Problem

High voltage semiconductor devices face challenges in integrating low voltage and high voltage regions on the same semiconductor substrate due to significant voltage differences, leading to design limitations and parasitic losses, particularly due to the low doping concentration in high voltage regions.

Innovation Solution

A high voltage semiconductor device design that includes a semiconductor substrate with distinct regions and interconnection structures, such as P-type junction isolation regions with higher doping concentrations, deep trenches, and buried doping layers to effectively separate and connect high and low voltage regions, preventing parasitic transistor operations and enhancing breakdown voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If a high voltage region with low doping concentration is formed to achieve high breakdown voltage, then the breakdown voltage is improved, but parasitic losses increase and device reliability deteriorates

Engineering Contradiction:
Improvebreakdown voltageVSAvoiddevice reliability
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The device is divided into distinct high voltage region and low voltage region with physical separation through isolation regions. The high voltage region uses low doping concentration for high breakdown voltage, while the low voltage region uses high doping concentration for low parasitic losses, eliminating the trade-off through spatial segmentation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Isolation regions are introduced as intermediary structures between the high voltage region and low voltage region. These isolation regions prevent parasitic transistor formation and reduce parasitic losses while allowing the high voltage region to maintain its low doping concentration for high breakdown voltage operation.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If deep trenches and isolation regions are added to separate high and low voltage regions, then parasitic losses are reduced and reliability is improved, but device complexity increases

Engineering Contradiction:
Improvedevice reliabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The semiconductor substrate is segmented into distinct functional regions (high voltage region, low voltage region, isolation regions) that can be independently optimized. This segmentation allows complex isolation structures to be systematically implemented while maintaining clear functional boundaries and simplifying design optimization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the device are given different doping concentrations and structural characteristics tailored to their specific functions. The isolation regions have specific doping profiles and geometries optimized for preventing parasitic effects, while high voltage and low voltage regions have their own optimized characteristics, allowing each local area to perform its function efficiently.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10600907B2High voltage semiconductor device
Publication Date: 2020.03.24 SK KEYFOUNDRY INC
  • US10600907B2 patent drawing
  • US10600907B2 patent drawing
  • US10600907B2 patent drawing

AI summary

A high voltage semiconductor device includes a semiconductor substrate, a first region, a second region, and an interconnection region. The first region includes an N-type first semiconductor region, an N-type drain region formed in the N-type first semiconductor region, a P-type first body region, an N-type source region formed in the P-type first body region, and a gate electrode formed between the N-type source region and the N-type drain region. The second region includes an N-type second semiconductor region, and a P-type second body region formed in the N-type second semiconductor region. The interconnection region is disposed between the first region and the second region, and includes a first insulation layer formed between the N-type first semiconductor region and the N-type second semiconductor region, a metal interconnection formed on the first insulation layer, and an isolation region formed in the substrate and disposed below the first insulation layer.