High Voltage Semiconductor Device With Segmented Wells
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Solution Overview
Problem
High voltage semiconductor devices, such as lateral diffused MOSFET transistors, are prone to failure due to unexpected high voltages from external inductive loads, leading to potential over-current and device burnout, as they often exceed the rated operating voltage.
Innovation Solution
The design incorporates a substrate with specific well regions and dopant concentrations, along with a gate structure and shallow trench isolation, to increase the total area of P-N junctions, allowing for higher current handling and improved voltage withstand capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a lateral diffused MOSFET transistor is used for high voltage operation, then the device can handle high voltage and high current, but it is vulnerable to unexpected high voltage from external inductive loads that exceeds the rated operating voltage, causing over-current and device burnout
Solution Approach 1:
The patent introduces a deep first-polarity well region (deep N-well in the embodiment) positioned closely around the first high voltage second-polarity well region (high voltage P-well). This deep well structure acts as a protective cushion that absorbs and dissipates unexpected high voltage surges before they can damage the main device structure, thereby preventing over-current and device burnout while maintaining high voltage handling capability
2Reliability
If the total area of P-N junctions is increased to handle higher current, then the device can withstand higher currents and unexpected high voltages, but the device structure becomes more complex with multiple well regions
Solution Approach 1:
The patent divides the protective structure into multiple segmented well regions: a first high voltage second-polarity well region for primary high voltage handling, and a deep first-polarity well region positioned closely around it for additional protection. This segmentation allows the device to achieve enhanced voltage withstand capability and larger effective P-N junction area while maintaining a structured and manageable device architecture
Data Source
AI summary
A high voltage semiconductor device is provided. A first-polarity buried layer is formed in the substrate. A first high voltage second-polarity well region is located over the first-polarity buried layer. A second-polarity base region is disposed within the first high voltage second-polarity well region. A source region is disposed within the second-polarity base region. A high voltage deep first-polarity well region is located over the first-polarity buried layer and closely around the first high voltage second-polarity well region. A first-polarity drift region is disposed within the high voltage deep first-polarity well region. A gate structure is disposed over the substrate. A second high voltage second-polarity well region is located over the first-polarity buried layer and closely around the high voltage deep first-polarity well region. A deep first-polarity well region is located over the first-polarity buried layer and closely around the second high voltage second-polarity well region.