High-Voltage Semiconductor Shield Layer Design
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Solution Overview
Problem
The existing high-voltage semiconductor devices face instability and reliability issues during switching due to N-type inversion phenomena and parasitic resistance components, which affect voltage withstanding characteristics and signal transmission in level shifting circuits.
Innovation Solution
A high-voltage semiconductor device with a level shifting circuit design that includes a phosphorus-doped n-type region, a high-side logic circuit region, and a shield layer connected to the OUT terminal, reducing parasitic capacitance and preventing N-type inversion by maintaining the shield layer's potential at ground level, even when the adjacent n region's potential rises to Vcc1.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a level shifting circuit uses a phosphorus-doped n-type region adjacent to the high-side logic circuit region, then the voltage withstanding capability is improved, but parasitic capacitance increases causing signal transmission issues
Solution Approach 1:
A shield layer is introduced as an intermediary component between the phosphorus-doped n-type region and the high-side logic circuit region. This shield layer, connected to ground potential, mediates the electrical interaction by providing a reference potential that reduces parasitic capacitance effects while allowing the n-type region to maintain its voltage blocking function. The shield layer acts as a buffer that prevents direct capacitive coupling between the high-voltage region and the logic circuit.
Solution Approach 2:
The potential of the shield layer is maintained at ground level (0V) while the adjacent n-type region potential varies between 0V and Vcc1. By controlling the shield layer potential parameter to remain constant at ground level, the parasitic capacitance is reduced because the voltage differential across the capacitive coupling is minimized during switching transitions, thereby reducing the harmful capacitive effects on signal transmission.
2Strength
If the shield layer potential follows the n region potential rise to Vcc1, then voltage blocking is improved, but N-type inversion occurs causing instability
Solution Approach 1:
The shield layer is maintained at equipotential with ground (0V) rather than following the n-type region potential. This equipotential condition creates a stable reference plane that prevents potential differences from inducing N-type inversion in the substrate. By keeping the shield layer at constant ground potential, the electric field distribution is controlled to prevent carrier inversion while still allowing the n-type region to perform voltage blocking when needed.
Solution Approach 2:
The shield layer connected to ground potential provides preliminary protection against N-type inversion by establishing a counteracting electric field. When the n-type region potential rises, the ground-connected shield layer creates an opposing field that prevents the substrate surface potential from becoming positive enough to cause N-type inversion, thereby preemptively preventing the instability issue before it occurs.
3Strength
If phosphorus doping concentration is increased to improve voltage withstanding, then breakdown voltage increases, but manufacturing complexity increases
Solution Approach 1:
Phosphorus doping is applied locally and selectively only in specific regions where voltage blocking is required, rather than uniformly across the entire substrate. The n-type region is created with specific phosphorus doping in targeted areas adjacent to the high-side logic circuit, while other regions maintain their original doping characteristics. This localized approach achieves the required breakdown voltage in critical areas without requiring high-dose uniform doping throughout the device, thereby simplifying the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design ensures stable voltage withstanding characteristics and reliable level shifting operations by preventing surface punch-through and avalanche breakdown, thereby enhancing the long-term reliability of high-voltage ICs.
Implementation Method 1
maintaining the shield layer's potential at ground level, even when the adjacent n region's potential rises to Vcc1
Implementation Method 2
a phosphorus-doped n-type region
Data Source
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AI summary
A withstand voltage region is formed to surround a logic circuit formation region. A high-voltage MOSFET (71, 72) for level shifting is formed in part of the withstand voltage region. A p- opening region (131) is formed between a drain region of the high-voltage MOSFET (71, 72) and the logic circuit formation region. A shield layer (300) connected to the negative electrode side of a power supply connected to the logic circuit formation region is disposed on the p- opening region (131). Thus, it is possible to provide a high-voltage semiconductor device including a level shifting circuit capable of making stable operation during the switching of a high-voltage IC and with long-term reliability.