High-Voltage Shifter Circuit for 3D NAND Transistor Degradation
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Solution Overview
Problem
In 3D NAND flash memory devices, high-voltage shifters face challenges due to transistor degradation under high gate-to-channel stress, leading to increased threshold voltage and reduced performance, which complicates the design and increases the size and complexity of the chip, necessitating a solution to reduce degradation and simplify the circuitry.
Innovation Solution
A high-voltage shifter circuit with a signal transfer circuit and first and second high-voltage control circuits is implemented, where a P-channel transistor transfers high voltage and a bias voltage is coupled for a specific time period, followed by a stress-relief signal to protect against degradation, using fewer transistors and reducing chip size and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional high-voltage shifters are used in 3D NAND flash memory, then high-voltage signal transfer is achieved, but transistor degradation occurs under high gate-to-channel stress leading to increased threshold voltage and reduced performance
Solution Approach 1:
The patent applies preliminary action by coupling a bias voltage to the P-channel transistor before high-voltage stress occurs, and then applying a stress-relief signal afterward. This preventive approach prepares the transistor for high-voltage operation and then actively reduces degradation, maintaining threshold voltage stability without requiring complex circuit redesign
Solution Approach 2:
The patent changes the electrical parameters applied to the transistor by introducing time-dependent bias voltages and stress-relief signals. By controlling the duration and magnitude of these voltage signals, the transistor operates reliably under high-voltage conditions while minimizing degradation, resolving the contradiction between reliability and complexity
2Reliability
If compensation circuits are added to address transistor degradation, then transistor performance stability is improved, but the size and complexity of the chip increases
Solution Approach 1:
The patent merges the degradation protection function into the existing high-voltage shifter circuit by using the same P-channel transistor and control signals for both signal transfer and stress relief. This integration achieves transistor performance stability without adding separate compensation circuits, thereby avoiding increased chip layout area
Solution Approach 2:
The control circuits in the patent serve multiple functions: they manage high-voltage signal transfer, apply bias voltages for protection, and provide stress-relief signals. This multi-functionality allows the circuit to maintain transistor reliability while minimizing the additional area required, as the same infrastructure is used for multiple purposes
3Reliability
If more transistors are used to compensate for degradation, then transistor performance stability is improved, but the number of transistors and circuit complexity increase
Solution Approach 1:
The patent implements self-service by having the existing P-channel transistor protect itself from degradation through the application of bias voltages and stress-relief signals controlled by the circuit. This approach maintains transistor performance stability without requiring additional transistors for compensation, thereby reducing circuit complexity compared to traditional compensation methods
Data Source
AI summary
Discussed herein are systems and methods for protecting against transistor degradation in a high-voltage (HV) shifter to transfer an input voltage to an access line, such as a global wordline. An embodiment of a memory device comprises memory cells and a HV shifter circuit that includes a signal transfer circuit, and first and second HV control circuits. The signal transfer circuit includes a P-channel transistor to transfer a high-voltage input to an access line. The first HV control circuit couples a bias voltage to the P-channel transistor for a first time period, and the second HV control circuit couples a stress-relief signal to the P-channel transistor for a second time period, after the first time period, to reduce degradation of the P-channel transistor. The transferred high voltage can be used to charge the access line to selectively read, program, or erase memory cells.