High-Voltage Switch With Symmetrical Charge-Pump Ripple Reduction

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Solution Overview

Problem

High-voltage switches in flash memories experience significant output ripple, which worsens the programmed distributions of threshold voltages, leading to decreased noise margin and potential read failures, especially in multilevel memory operations.

Innovation Solution

A high-voltage switch design incorporating a voltage-multiplying circuit with symmetrical charge-storage elements and a charge-pump mechanism, utilizing low-voltage NMOS and PMOS transistors to minimize ripple by ensuring the voltage difference across the multiplier stage never exceeds the supply voltage, thereby stabilizing the output voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If a voltage-multiplying circuit with asymmetrical charge-storage elements is used, then high-voltage transfer is achieved, but output ripple increases significantly

Engineering Contradiction:
Improvehigh-voltage transfer capabilityVSAvoidoutput ripple
Core Design Contradiction:
PowerVSObject-generated harmful factors

Solution Approach 1:

The patent applies asymmetry in reverse by using symmetrical charge-storage elements (first and second capacitors with equal values) in the voltage-multiplying circuit. This symmetry ensures that both capacitors charge and discharge at the same rate, canceling out ripple effects that would otherwise occur with asymmetrical elements. The symmetrical configuration maintains the high-voltage transfer capability while eliminating the harmful output ripple.

Inventive Principle:
Principle #4Asymmetry

2Reliability

If high-voltage P-channel transistors are used in the voltage-multiplying circuit, then complete high-voltage transfer is ensured, but device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improvecomplete high-voltage transferVSAvoidcircuit structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the parameter of transistor type from high-voltage P-channel to low-voltage N-channel transistors. By using low-voltage N-channel transistors in conjunction with the symmetrical voltage-multiplying circuit, the design achieves complete high-voltage transfer without requiring complex high-voltage P-channel devices. This parameter change simplifies the circuit structure and reduces manufacturing difficulty while maintaining reliability.

Inventive Principle:
Principle #35Parameter changes

3Speed

If the voltage difference across the multiplier stage exceeds the supply voltage, then faster voltage transfer speed is achieved, but output ripple increases

Engineering Contradiction:
Improvevoltage transfer speedVSAvoidoutput ripple
Core Design Contradiction:
SpeedVSObject-generated harmful factors

Solution Approach 1:

The patent implements dynamic control of the voltage difference across the multiplier stage by using a clock signal to alternately charge and discharge the symmetrical capacitors. This dynamic operation allows the circuit to maintain an optimal voltage difference that does not exceed the supply voltage, thereby achieving fast voltage transfer speed while preventing excessive output ripple through controlled, periodic operation.

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design achieves a reduction in output ripple by up to 66%, maintaining comparable rise time performance while allowing the use of low-voltage transistors, reducing circuit area, and enabling adaptable high-voltage transfer speeds through cascaded voltage-doubler circuits and adjustable clock frequencies.

Implementation Method 1

a first capacitor (5) having a first terminal connected to the internal node (7), and a second terminal connected to the second input terminal (IN2) via interposition of a first logic inverter (8), and consequently receiving the negated clock signal (CK)

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

The second NMOS transistor (3) is diode-connected, and has its gate terminal connected to the third input terminal (IN3) via interposition of the third NMOS transistor (4), which in turn has its gate terminal connected to the internal node (7)

Methodology Applied
Scientific EffectBody effect:

Data Source

PatentUS7521983B2High-voltage switch with low output ripple for non-volatile floating-gate memories
Publication Date: 2009.04.21 MICRON TECHNOLOGY INC
  • US7521983B2 patent drawing
  • US7521983B2 patent drawing
  • US7521983B2 patent drawing

AI summary

A high-voltage switch has a high-voltage input terminal, receiving a high voltage, and an output terminal. A pass transistor, having a control terminal, is connected between the high-voltage input terminal and the output terminal. The output of a voltage-multiplying circuit of the charge-pump type is connected to the control terminal. The voltage-multiplying circuit is of a symmetrical type, has first and second charge-storage means, receiving a clock signal of a periodic type, and has a first circuit branch and a second circuit branch, which are symmetrical to one another and operate in phase opposition with respect to the clock signal.