High-Voltage Semiconductor Layout for Low-Capacitance Switching

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Solution Overview

Problem

High breakdown voltage ICs face issues with power loss and malfunction due to high switching frequency and dV/dt surges, which cause abnormal voltage drops and false signal generation, leading to short-circuits and incorrect turn-on/turn-off of IGBTs.

Innovation Solution

A semiconductor device with a breakdown voltage region and isolation region on a semiconductor substrate, where the breakdown voltage region is isolated by a high resistance element, reducing parasitic capacitance and output capacitance, and a driving circuit with high breakdown voltage transistors for level shifting, which reduces displacement currents and power loss.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If high breakdown voltage ICs are used for high-speed switching applications, then switching speed is improved, but parasitic capacitance and displacement currents cause malfunctions and power loss

Engineering Contradiction:
Improveswitching speedVSAvoidmalfunction resistance
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent segments the semiconductor device into distinct conductivity type regions (first conductivity type breakdown voltage region, second conductivity type breakdown voltage region) separated by an intrinsic semiconductor region. This segmentation isolates the high-voltage switching regions while reducing parasitic capacitance between them, enabling high-speed operation without malfunction. The intrinsic region acts as an electrical barrier that prevents displacement current from causing false signals.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intrinsic semiconductor region as an intermediary between the first and second conductivity type breakdown voltage regions. This intrinsic region serves as a mediator that electrically isolates the high-voltage switching regions, reducing parasitic capacitance and preventing displacement currents from causing malfunctions, while still allowing the device to achieve high breakdown voltage and fast switching.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Strength

If high breakdown voltage ICs are used, then breakdown voltage is improved, but parasitic capacitance increases causing power loss

Engineering Contradiction:
Improvebreakdown voltageVSAvoidpower loss
Core Design Contradiction:
StrengthVSLoss of energy

Solution Approach 1:

The patent divides the semiconductor structure into segmented conductivity type regions (first conductivity type, second conductivity type) separated by an intrinsic region. This segmentation reduces the parasitic capacitance between high-voltage regions compared to a monolithic structure, thereby reducing power loss while maintaining high breakdown voltage capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different conductivity types locally in different regions of the semiconductor device. The first conductivity type breakdown voltage region and second conductivity type breakdown voltage region are positioned adjacently with an intrinsic region between them, creating local variations in electrical properties that reduce parasitic capacitance and power loss while maintaining overall high breakdown voltage.

Inventive Principle:
Principle #3Local quality

3Speed

If load resistance is reduced to increase switching speed, then switching response speed is improved, but displacement currents increase causing malfunctions

Engineering Contradiction:
Improveswitching response speedVSAvoiddisplacement current
Core Design Contradiction:
SpeedVSObject-generated harmful factors

Solution Approach 1:

The intrinsic semiconductor region acts as an intermediary that blocks displacement current from causing malfunctions. By placing this intrinsic region between the conductivity type regions, the patent allows load resistance to be reduced for faster switching while the intrinsic region prevents the resulting displacement currents from generating false signals.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent converts the harmful effect of displacement current (which increases when load resistance is reduced) into a beneficial outcome. The intrinsic semiconductor region is designed to tolerate and isolate the displacement current, preventing it from causing malfunctions while allowing the load resistance to be reduced for faster switching response.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enables high switching response speed, reduced power loss, and minimized malfunctions by lowering output capacitance and displacement currents, allowing for efficient operation under high switching frequencies.

Implementation Method 1

High breakdown voltage ICs face malfunctions and increased power loss due to parasitic capacitance and displacement currents caused by dV/dt surges

Methodology Applied
Scientific EffectParasitic capacitance: Parasitic Capacitance

Implementation Method 2

a first conductivity type semiconductor region formed between the drift region and the other region so as to be in contact with the isolation region and the semiconductor substrate and to isolate the drift region and the other region from each other

Methodology Applied
Scientific EffectElectrical isolation: Electrical Resistance

Data Source

PatentUS20120286829A1Semiconductor device and driving circuit
Publication Date: 2012.11.15 FUJI ELECTRIC CO LTD
  • US20120286829A1 patent drawing
  • US20120286829A1 patent drawing
  • US20120286829A1 patent drawing

AI summary

A high breakdown voltage semiconductor device includes: an n− type region (101) surrounded by a p− well region (102) on a p− type silicon substrate (100); a drain n+ region (103) connected to a drain electrode (120); a p base region (105) formed so as to surround the drain n+ region (103); a source n+ region (114) formed in the p base region (105); and a p− region (131) for isolating the n− type region (101) into an n− type region (101a) including the drain n+ region (103), and an n− type region (101b) not having the drain n+ region (103). The n− type region (101b) is connected to the drain electrode (120) or the drain n+ region (103) via an n offset region (104) or a polysilicon (304) which is a high resistance element.