High-Voltage Transistor Layout to Reduce Interface Charge Trapping

Solution Overview

Problem

High-voltage fin-based transistors experience charge trapping at interfaces between dielectric regions and fin structures, leading to unstable performance and reduced operational lifetime due to increased surface area contact with dielectric layers.

Innovation Solution

Incorporating planar active regions instead of multiple fin structures to reduce the interface surface area between silicon-based active regions and oxide-based dielectric layers, thereby minimizing charge trapping.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple fin structures are used to increase control over channel regions, then switching performance is improved, but interface surface area with dielectric layers increases leading to charge trapping

Engineering Contradiction:

Improveswitching performanceVSAvoidinterface surface area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The invention segments the active region into multiple fins only where needed for channel control under the gate structure, while keeping the source and drain active regions as unified planar structures. This segmentation approach maintains the benefits of multiple fins for channel control while avoiding the charge trapping issues that would result from segmenting the entire active region including source and drain areas.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention applies different structural qualities to different regions: multiple fins are used locally under the gate where channel control is needed, while planar structures are used in the source and drain regions where charge trapping would be problematic. This local differentiation resolves the contradiction by applying the appropriate structure in each location.

Inventive Principle:

Principle #3Local quality

2Duration of action of stationary object

If multiple fin structures are used to increase control over channel regions, then operational lifetime is reduced due to charge trapping, but using planar structures would improve lifetime

Engineering Contradiction:

Improveoperational lifetimeVSAvoidperformance stability

Core Design Contradiction:

Duration of action of stationary objectVSReliability

Solution Approach 1:

The invention segments the active region into multiple fins only where needed for channel control under the gate structure, while keeping the source and drain active regions as unified planar structures. This segmentation approach maintains the benefits of multiple fins for channel control while avoiding the charge trapping issues that would result from segmenting the entire active region including source and drain areas.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention applies different structural qualities to different regions: multiple fins are used locally under the gate where channel control is needed, while planar structures are used in the source and drain regions where charge trapping would be problematic. This local differentiation resolves the contradiction by applying the appropriate structure in each location.

Inventive Principle:

Principle #3Local quality

3Object-generated harmful factors

If planar active regions are used to reduce interface surface area, then charge trapping is minimized, but control over channel region may be reduced

Engineering Contradiction:

Improvecharge trappingVSAvoidchannel control

Core Design Contradiction:

Object-generated harmful factorsVSReliability

Solution Approach 1:

The invention segments the active region into multiple fins only where needed for channel control under the gate structure, while keeping the source and drain active regions as unified planar structures. This segmentation approach maintains the benefits of multiple fins for channel control while avoiding the charge trapping issues that would result from segmenting the entire active region including source and drain areas.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention applies different structural qualities to different regions: multiple fins are used locally under the gate where channel control is needed, while planar structures are used in the source and drain regions where charge trapping would be problematic. This local differentiation resolves the contradiction by applying the appropriate structure in each location.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS20230420504A1High-voltage semiconductor devices and methods of formation

Publication Date: 2023.12.28 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A high-voltage transistor may include a planar active region for a first source/drain active region, a second source/drain active region, and/or a channel active region. The planar active region(s) are included instead of a plurality of fin active regions to reduce the amount of surface area of the active regions in the high-voltage transistor that is in contact with surrounding dielectric layers of the high-voltage transistor. In other words, the planar active region(s) reduce the interface surface area between the silicon-based active regions of the high-voltage transistor and the surrounding oxide-based dielectric layers. The reduced interface surface area may reduce the occurrence of charge trapping in the high-voltage transistor, which may result in increased performance stability for the high-voltage transistor and/or may provide increased operational lifetime of the high-voltage transistor.