High-Voltage Transistor Gate Structure for Higher Collapse Voltage
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Solution Overview
Problem
Existing semiconductor fabrication technologies face challenges in increasing the collapse voltage of high-voltage transistors, as the insulation between the field plate and the substrate is difficult to enhance without compromising the fabrication process compatibility.
Innovation Solution
A semiconductor device structure is developed, which includes a substrate with multiple gate insulating layers and a field plate layer with a depleted region, providing improved insulation capability between the field plate and the substrate, thereby increasing the collapse voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the insulating layer between the field plate and the substrate is increased to prevent transistor collapse, then the collapse voltage increases, but it becomes difficult to implement under a fabrication process compatible with general fabrication processes
Solution Approach 1:
The insulating structure is segmented into multiple functional layers: a first insulating layer (thinner) directly under the field plate for process compatibility, and a second insulating layer (thicker) adjacent to the drain region for enhanced electrical isolation and collapse voltage improvement. This segmentation allows each layer to be optimized for its specific function while maintaining overall fabrication compatibility.
Solution Approach 2:
Different insulating layer configurations are applied to different regions: the first insulating layer uses a thickness suitable for general fabrication processes in the field plate region, while the second insulating layer provides increased thickness specifically in the drain region where high electric field isolation is critical for preventing transistor collapse.
2Reliability
If a thicker insulating layer is used between the field plate and the substrate, then the insulation capability improves, but the fabrication process complexity increases
Solution Approach 1:
The insulating structure is divided into a first insulating layer and a second insulating layer with different thicknesses and functions. The first layer maintains compatibility with standard fabrication processes, while the second layer provides enhanced insulation only where needed, avoiding the need to increase thickness across the entire structure and thus limiting fabrication process complexity.
Solution Approach 2:
The thicker second insulating layer is localized specifically to the drain region where high electric field isolation is required, rather than uniformly increasing insulating layer thickness across all regions. This localized approach improves insulation capability where critical while minimizing additional fabrication process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure effectively enhances the insulation capability between the field plate and the substrate, leading to an increased collapse voltage and improved performance of high-voltage transistors, while maintaining compatibility with standard fabrication processes.
Implementation Method 1
A field plate layer is disposed on the dielectric layer and includes a depleted region, and is at least disposed on the bottom dielectric layer. The depleted region of the field plate layer provides an insulation capability to the dielectric layer.
Data Source
AI summary
A structure of a semiconductor device, including a substrate, is provided. A first gate insulating layer is disposed on the substrate. A second gate insulating layer is disposed on the substrate. The second gate insulating layer is thicker than the first gate insulating layer and abuts the first gate insulating layer. A gate layer has a first part gate on the first gate insulating layer and a second part gate on the second gate insulating layer. A dielectric layer has a top dielectric layer and a bottom dielectric layer. The top dielectric layer is in contact with the gate layer, and the bottom dielectric layer is in contact with the substrate. A field plate layer is disposed on the dielectric layer and includes a depleted region, and is at least disposed on the bottom dielectric layer. A method for fabricating the semiconductor device is provided too.