High Voltage Transistor ESD Protection Holding Voltage
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Solution Overview
Problem
Conventional high voltage transistors used in electrostatic discharge (ESD) protection circuits have a low holding voltage and are prone to latchup, leading to overheating and malfunction due to their snapback characteristic and limited size, especially when dealing with high voltages like 60, 80, or 100 volts, which is exacerbated by the need for multiple stacked transistors.
Innovation Solution
A high voltage transistor design featuring a substrate with a high voltage well, multiple doped regions, and strategically placed second base regions that enhance the holding voltage and reduce trigger voltage, allowing for a single transistor to meet ESD voltage requirements while minimizing device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple low voltage LDNMOS transistors are stacked to increase holding voltage, then the holding voltage becomes greater than the supply voltage, but the chip area is significantly increased
Solution Approach 1:
The transistor is segmented into multiple conductivity type regions (first conductivity type and second conductivity type regions) within a single transistor structure. This segmentation allows the transistor to achieve high holding voltage through the series connection of multiple junctions internally, without requiring multiple external transistor stacks, thereby reducing chip area while maintaining reliability.
Solution Approach 2:
The patent embeds multiple doped regions and conductivity type regions within a single transistor structure, creating a nested configuration where first doped regions, second doped regions, and base regions are positioned in specific spatial relationships. This nesting allows the single transistor to function equivalently to multiple stacked transistors, achieving high holding voltage without increasing chip area.
2Ease of operation
If the holding voltage is less than the supply voltage, then the ESD clamp circuit can be triggered, but the latchup is induced and high current damages the internal circuit
Solution Approach 1:
The patent carefully controls and adjusts key parameters including doping concentrations (first doping concentration, second doping concentration, third doping concentration), region dimensions, and spatial positions of doped regions. By optimizing these parameters, the transistor achieves a holding voltage greater than the supply voltage while maintaining appropriate trigger voltage, thus enabling ESD protection without inducing latchup.
Solution Approach 2:
Different regions of the transistor are assigned different doping concentrations and conductivity types to create localized electrical characteristics. The first doped regions have different properties than the second doped regions, allowing the transistor to exhibit different voltage characteristics at different locations, achieving both trigger capability and latchup prevention through localized property optimization.
Data Source
AI summary
The present invention provides a high voltage transistor including a substrate, a first base region having a first conductivity type, and a first doped region, a second doped region, a second base region and a third doped region having a second conductivity type complementary to the first conductivity type. The first base region, the second doped region, the second base region and the third doped region are disposed in the substrate, and the first doped region is disposed in the substrate. The third doped region, the second base region and the second doped region are stacked sequentially, and the doping concentrations of the third doped region, the second base region and the second doped region gradually increase.