High Voltage Transistor Fabrication Using Lightly-Doped Drain Regions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing high voltage devices, such as programming Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) nonvolatile memory, require medium high or high programming voltages, necessitating customized doping profiles and thicker gate oxide layers, which complicates integration into conventional CMOS fabrication processes and lowers yield.
Innovation Solution
A high voltage transistor is fabricated using conventional CMOS processes with lightly-doped regions surrounding the drain and source areas, extending inwardly from the edges of shallow trench isolation regions, and a salicide block layer is introduced to reduce electric fields and enhance junction breakdown voltage without additional masking steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If customized doping profiles and thicker gate oxide layers are used to achieve sufficient breakdown voltage, then junction breakdown voltage is improved, but device complexity and fabrication process complexity increase
Solution Approach 1:
The patent applies local quality by creating lightly-doped drain regions with specific doping concentrations (1E16 to 1E18 atoms/cm³) that are lighter than the substrate, and by forming rounded corners at the drain region with radii of curvature of 0.5 micrometers or more. These localized modifications in the drain region specifically address breakdown voltage requirements without requiring customized doping profiles throughout the entire device, thus improving reliability while avoiding excessive fabrication complexity.
2Reliability
If customized doping profiles and thicker gate oxide layers are used to achieve sufficient breakdown voltage, then junction breakdown voltage is improved, but manufacturing yield decreases
Solution Approach 1:
The patent changes the doping concentration parameter in the drain region to be lighter (1E16 to 1E18 atoms/cm³) compared to the substrate, and modifies the geometric parameter by forming rounded corners with radii of 0.5 micrometers or more. These parameter changes achieve sufficient breakdown voltage (5V to 10V or higher) using standard CMOS gate oxide thickness, thereby improving reliability while maintaining compatibility with existing fabrication processes and preserving manufacturing yield.
3Ease of manufacture
If standard CMOS processes are used without additional masking steps, then ease of manufacture is improved, but achieving sufficient breakdown voltage becomes difficult
Solution Approach 1:
The patent implements preliminary action by forming rounded corners at the drain region before final device completion, and by pre-establishing the lightly-doped drain regions with appropriate doping concentrations. These preliminary structural modifications create favorable electric field distributions that enable sufficient breakdown voltage (5V to 10V or higher) to be achieved using standard CMOS processes without requiring additional masking steps, thus maintaining ease of manufacture while improving reliability.
Data Source
AI summary
A method for fabricating a high-voltage transistor on a semiconductor substrate includes defining and forming shallow trench isolation regions for all of the transistors, defining and forming well regions for all of the transistors, forming a gate oxide layer in the well regions for all of the transistor, forming gates for all of the transistors over the gate oxide layer, implanting a dopant to form lightly-doped drain regions for all of the transistors, the lightly-doped drain regions for at least drains of the high-voltage transistors being spaced apart from an inner edge of the shallow trench isolation regions, forming gate spacers at sides of the gates of all of the transistors, and implanting a dopant to form sources and drains for all of the transistors, the drains of the high-voltage transistors being formed completely surrounded by the lightly-doped drain regions of the high-voltage transistors.