High Voltage Well Structure for Parasitic Latch-Up Suppression
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Solution Overview
Problem
High voltage devices experience latch-up issues due to parasitic transistors, leading to malfunction and reduced safe operation area, which existing technologies fail to adequately address.
Innovation Solution
The design incorporates a high voltage device structure with specific well configurations and doping profiles, including a high voltage well with higher impurity concentration than the second deep well, to suppress parasitic transistor current gain and prevent latch-up, thereby increasing the safe operation area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional well structures are used in high voltage devices, then device simplicity is maintained, but parasitic transistor latch-up occurs reducing safe operation area
Solution Approach 1:
The device divides the well structure into multiple segmented regions: a first deep well, a second deep well, and a high voltage well positioned between them. This segmentation creates distinct functional zones that independently control parasitic transistor behavior, preventing latch-up while maintaining overall device functionality.
Solution Approach 2:
The high voltage well is strategically positioned only in the drift region between the source and drain, with specific doping characteristics (higher impurity concentration than the second deep well). This local quality enhancement targets the critical area where parasitic transistors form, suppressing latch-up current gain without affecting other device regions.
2Reliability
If high voltage well with higher impurity concentration is introduced, then parasitic transistor current gain is suppressed, but device structure becomes more complex
Solution Approach 1:
The high voltage well employs a specific doping parameter configuration where the impurity concentration is higher than that of the second deep well. This parameter change directly suppresses the base current and current gain of parasitic transistors, preventing latch-up while the doping profile is established through controlled manufacturing processes.
3Reliability
If multiple deep wells are configured, then parasitic transistor latch-up is prevented, but manufacturing process becomes more difficult
Solution Approach 1:
The first deep well and second deep well are formed in advance during the device fabrication process, establishing the foundational structure before final device assembly. This preliminary action ensures proper well formation and electrical isolation, preventing latch-up issues that would be difficult to correct later in manufacturing.
Data Source
AI summary
A high voltage device includes: a semiconductor layer, an isolation structure, a first deep well, a second deep well, a drift well, a first well, a second well, a body region, a body contact, a high voltage well, a gate, and a source and a drain. The high voltage well is formed in the second deep well, and the high voltage well is not in contact with any of the first deep well, the first well, and the second well, wherein at least part of the high voltage well is located right below all of a drift region to suppress a latch-up current generated in the high voltage device.