Iterative Estimation Hardware With Higher-Order Polynomial Logic
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Solution Overview
Problem
Existing hardware logic for evaluating functions like the reciprocal, square root, or cube root of an input number using iterative methods suffers from rounding errors that accumulate due to slow convergence and requires significant hardware resources.
Innovation Solution
Implementing a function estimation hardware logic unit within a processor's execution pipeline that uses a mth-order polynomial with rational coefficients (m>2) to achieve faster convergence, reducing the number of iterations needed and minimizing rounding errors, thereby improving accuracy and reducing hardware size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional iterative methods (e.g., Newton-Raphson) are used to evaluate functions in hardware, then the hardware can be reused for multiple iterations, but rounding errors accumulate and convergence is slow, requiring significant hardware resources
Solution Approach 1:
The patent changes the mathematical parameters of the iterative method by using mth-order polynomials with m>2 instead of traditional second-order methods. This parameter change in the convergence order directly improves accuracy while reducing the number of iterations needed, thereby reducing hardware resource requirements
Solution Approach 2:
The patent implements dynamic adjustment of iteration count based on convergence criteria. The hardware monitors the change in estimate between iterations and terminates when a threshold is met, optimizing the balance between accuracy and hardware resource usage in real-time
2Productivity
If traditional iterative methods are used, then hardware can be reused for multiple iterations trading throughput for area, but the slow convergence requires many iterations and accumulates rounding errors
Solution Approach 1:
By increasing the order parameter m of the polynomial method, the patent achieves faster convergence rates. This parameter change reduces the number of iterations required for a given accuracy level, thereby improving throughput while maintaining or enhancing precision
Solution Approach 2:
The patent incorporates feedback mechanisms where each iteration's output is fed back as input for the next iteration. The convergence is monitored through feedback comparison, and the iteration process dynamically adjusts based on the achieved precision, optimizing throughput
3Measurement precision
If more iterations are performed to improve accuracy, then rounding errors accumulate less, but hardware resources and time increase
Solution Approach 1:
The patent changes the convergence parameter from traditional second-order to mth-order (m>2) polynomial methods. This parameter change achieves faster convergence, reducing both the time required and the number of iterations needed to reach a given accuracy level
Solution Approach 2:
The patent uses preliminary estimation techniques to obtain an initial guess that is closer to the final result. This preliminary action reduces the number of full iterations required, thereby reducing both time and computational resources while maintaining accuracy
Data Source
AI summary
A function estimation hardware logic unit may be implemented as part of an execution pipeline in a processor. The function estimation hardware logic unit is arranged to calculate, in hardware logic, an improved estimate of a function of an input value, d, where the function is given by1/di.The hardware logic comprises a plurality of multipliers and adders arranged to implement a mth-order polynomial with coefficients that are rational numbers, where m is not equal to two and in various examples m is not equal to a power of two. In various examples i=1, i=2 or i=3. In various examples m=3.