High-k Gate Dielectric Mixture for CMOS Threshold Voltage Symmetry
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Solution Overview
Problem
High-k gate dielectric materials in CMOS devices exhibit Fermi-pinning effects, leading to asymmetric threshold voltages and low mobility, making it difficult to achieve symmetric threshold voltages for PMOS and NMOS transistors.
Innovation Solution
A method involving the deposition of a high-k dielectric material over a silicon dioxide or silicon oxynitride layer, followed by annealing to combine a portion of the high-k material with the silicon dioxide or silicon oxynitride, forming a gate dielectric mixture that eliminates Fermi-pinning and allows for symmetric threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If high-k gate dielectric material is used, then gate leakage current is reduced, but Fermi-pinning effect causes asymmetric threshold voltage and low mobility
Solution Approach 1:
The gate dielectric is segmented into multiple layers: a first dielectric layer (SiO2 or SiON) and a second dielectric layer (high-k material). This segmentation allows the first layer to provide good interface properties while the second layer provides high dielectric constant, thereby reducing gate leakage without causing Fermi-pinning effects that lead to asymmetric threshold voltage.
Solution Approach 2:
The gate dielectric uses a composite structure combining SiO2 or SiON with high-k dielectric material. This composite approach leverages the advantages of both materials: the SiO2/SiON provides a stable interface with the semiconductor substrate, while the high-k material provides superior leakage characteristics, achieving both low gate leakage and symmetric threshold voltage.
2Loss of energy
If high-k gate dielectric material is used, then gate leakage current is reduced, but device mobility decreases due to Fermi-pinning effect
Solution Approach 1:
By segmenting the gate dielectric into a first layer (SiO2 or SiON) and a second layer (high-k material), the interface between the high-k material and semiconductor substrate is mediated by the first layer. This prevents direct Fermi-pinning interaction while maintaining the low leakage benefits of the high-k material, thereby preserving device mobility.
Solution Approach 2:
The first dielectric layer (SiO2 or SiON) acts as an intermediary layer between the semiconductor substrate and the high-k dielectric material. This intermediary prevents the Fermi-pinning effect from occurring at the substrate-dielectric interface, allowing high mobility to be maintained while still achieving low gate leakage through the high-k material.
3Quantity of substance
If high-k gate dielectric material is used, then dielectric constant increases, but threshold voltage control becomes difficult
Solution Approach 1:
Segmenting the gate dielectric into two layers enables independent optimization of each layer's properties. The first layer thickness and composition can be controlled to achieve desired threshold voltage, while the second layer provides the high dielectric constant. This segmentation decouples threshold voltage control from dielectric constant selection.
Solution Approach 2:
By changing the structure from a single-layer high-k dielectric to a two-layer structure, the parameters governing threshold voltage (primarily the first layer properties) and dielectric constant (primarily the second layer properties) can be independently adjusted. This allows precise threshold voltage control while maintaining high dielectric constant.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method results in CMOS devices with a high-k gate dielectric material that reduces gate leakage current and achieves symmetric threshold voltages for PMOS and NMOS transistors, improving device performance and mobility.
Implementation Method 1
annealing to combine a portion of the high-k material with the silicon dioxide or silicon oxynitride, forming a gate dielectric mixture
Data Source
AI summary
Methods of forming transistor devices and structures thereof are disclosed. A first dielectric material is formed over a workpiece, and a second dielectric material is formed over the first dielectric material. The workpiece is annealed, causing a portion of the second dielectric material to combine with the first dielectric material and form a third dielectric material. The second dielectric material is removed, and a gate material is formed over the third dielectric material. The gate material and the third dielectric material are patterned to form at least one transistor.