High-k Gate Stack Segmentation for Leakage Reduction
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to balance gate dielectric reliability and performance, as increasing dielectric thickness improves reliability but decreases performance, and decreasing thickness enhances performance but reduces reliability, especially in scaled-down MOSFET devices. Additionally, crystallization of high-k gate oxides leads to detrimental effects such as oxygen diffusion, surface roughness, and enhanced gate leakage.
Innovation Solution
A method involving a high-k bilayer or nanolaminate structure with a crystallized bottom portion and an amorphous top portion, achieved through a millisecond anneal process with a substrate preheat temperature below 600°C, which crystallizes the lower portion of the high-k dielectric material while maintaining the top layer in an amorphous state, and integrating La2O3 doping to form dipoles for threshold voltage tunability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of a dielectric material stack is increased, then reliability of the semiconductor device is improved, but performance decreases
Solution Approach 1:
The gate dielectric stack is segmented into multiple layers with different materials (e.g., HfO2, SiO2, Al2O3) and different thicknesses. The bottom layer provides reliability through thickness while the top layer maintains performance through thinner dimensions, resolving the contradiction between reliability and performance
Solution Approach 2:
The patent employs composite dielectric structures combining multiple materials with different electrical and physical properties. This composite approach allows the stack to achieve both high reliability (through the thicker, more robust bottom layers) and high performance (through the thinner, higher-quality top layers) simultaneously
2Productivity
If the thickness of a dielectric material stack is decreased, then performance is improved, but reliability decreases
Solution Approach 1:
The gate dielectric is segmented into functional layers where the top thin layer delivers performance and the bottom thicker layer ensures reliability, allowing the overall structure to achieve both goals simultaneously
Solution Approach 2:
Different regions of the gate dielectric stack are assigned different qualities: the top layer has optimized thickness for performance while the bottom layer has increased thickness for reliability, applying local quality differentiation to resolve the contradiction
3Manufacturing precision
If high-k gate oxide is crystallized, then certain material properties are improved, but oxygen diffusion, surface roughness, and gate leakage increase
Solution Approach 1:
The gate dielectric stack is segmented such that only the bottom layer undergoes crystallization while the top layer remains amorphous. This segmentation allows the crystalline layer to provide material stability while the amorphous layer prevents oxygen diffusion and reduces gate leakage
Solution Approach 2:
Different crystalline states are applied to different layers: the bottom layer is crystallized for material property improvement while the top layer remains amorphous to minimize harmful effects like oxygen diffusion and gate leakage, applying local quality differentiation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves negative and positive bias temperature instability (NBTI/PBTI) lifetimes, reduces gate leakage, and provides superior threshold voltage tunability, resulting in enhanced reliability and performance for sub-20 nm planar and FinFET technologies.
Implementation Method 1
a millisecond anneal to crystallize a lower portion of a high-k dielectric material with a top layer of the high-k dielectric material being amorphous
Implementation Method 2
conducting laser annealing or other millisecond-scale (mSec) annealing of the implanted extension regions either prior, during, or after a more conventional, second-scale Rapid Thermal Anneal (RTA)
Implementation Method 3
The dopants are activated by conducting laser annealing or other millisecond-scale (mSec) annealing of the implanted extension regions
Data Source
AI summary
Semiconductor structures and methods of fabricating the same using interrupted deposition processes and multiple laser anneals are provided. The structure includes a high-k gate stack with a high-k bilayer or nanolaminate where a bottom portion of the bilayer is crystallized while a top portion of the bilayer is amorphous.