High-k Gate Dielectric Threshold Voltage Control
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Solution Overview
Problem
The use of high-k gate dielectric layers in MISFETs leads to an increase in threshold voltage, which negatively affects transistor driving performance, as metals in the dielectric layer react with silicon and implanted ions, necessitating precise control of the threshold voltage.
Innovation Solution
A semiconductor device design featuring low-concentration impurity layers in the channel portion of the well, with a high-k gate dielectric layer and a gate electrode, along with source/drain regions, allows for accurate control of the threshold voltage by forming p-type and n-type low-concentration layers and using specific ion implantation and heat treatment processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high-k gate dielectric layer is used as the gate dielectric layer, then the gate leakage current is reduced, but the threshold voltage of the MISFET rises excessively
Solution Approach 1:
The patent applies local quality by forming a low-concentration impurity layer specifically in the channel portion of the well, creating a localized region with different impurity concentration. This local modification allows the high-k gate dielectric layer to be used (reducing gate leakage) while the localized low-concentration region compensates for the threshold voltage increase through controlled impurity distribution.
2Volume of moving object
If the thickness of silicon oxide film is reduced to achieve high-speed performance and size reduction, then the device size is reduced, but the gate leakage current increases
Solution Approach 1:
The patent changes the material parameter by transitioning from silicon oxide film to high-k gate dielectric layer, which has a higher dielectric constant. This parameter change allows maintaining thin film thickness (for small device size) while achieving lower gate leakage current due to the higher dielectric constant providing better insulation at reduced thickness.
3Stability of the object's composition
If metals in high-k gate dielectric layer react with silicon and implanted ions, then the dielectric properties are compromised, but threshold voltage control becomes difficult
Solution Approach 1:
The patent applies preliminary anti-action by forming the low-concentration impurity layer in advance, before the adverse reactions between metals and silicon/ions fully occur. This pre-formed layer creates a buffer region that counteracts the threshold voltage shifts caused by subsequent reactions, allowing better control of threshold voltage despite the inherent reactivity issues.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise control of the threshold voltage in MISFETs with high-k gate dielectric layers, improving transistor performance by reducing the adverse reactions between metals and silicon or ions, thereby maintaining optimal driving performance.
Implementation Method 1
A high-k gate dielectric layer having a higher dielectric constant than a silicon oxide film
Implementation Method 2
implanting a first conductive type impurity into a substrate
Implementation Method 3
performing a heat treatment to diffuse the implanted ions
Data Source
AI summary
A semiconductor device having a high-K gate dielectric layer includes a p-type well that is formed in an upper layer of a silicon substrate. Arsenic ions are implanted into an extreme surface layer of the p-type well and a heat treatment is performed to form a p-type low-concentration layer. A HfAlOx film and a polycrystalline silicon layer are laminated on the substrate. A gate electrode is formed by patterning the polycrystalline silicon layer. After a n-type extension region is formed by implanting arsenic ions by using the gate electrode as a mask, sidewall spacers are formed on sides of the gate electrode. Arsenic ions are implanted by using the sidewall spacers and the gate electrode as masks, whereby n-type source/drain regions are formed.