High-k Buried Insulating Layer for SOI Bonding and Leakage Control
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Solution Overview
Problem
The miniaturization of semiconductor components, such as MOS transistors, leads to short channel effects due to parasitic electrostatic fields, which are difficult to mitigate with conventional SOI structures as the thickness of the buried insulating layer is reduced, causing bonding defects and current leakage issues during the Smart Cut™ technology process.
Innovation Solution
Implementing a buried insulating layer made of high k type dielectric materials with a dielectric constant greater than silicon dioxide, allowing for a sufficient thickness to ensure good bonding and minimize short channel effects without compromising the bonding quality, by using materials like AlN, Si3N4, or TiO2, which have a capacitance equivalent to a silicon dioxide layer with a thickness of less than or equal to 30 nm.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the buried insulating layer is reduced to improve coupling between gate and channel, then short channel effects are reduced, but bonding quality deteriorates and manufacturing defects increase
Solution Approach 1:
The patent changes the dielectric constant parameter of the insulating layer material from conventional SiO2 (k≈3.9) to high-k materials (k>5 such as AlN, Si3N4, TiO2). This parameter change allows achieving the same or better coupling effect (capacitance) with a thicker layer, thereby resolving the contradiction between improving coupling and maintaining bonding quality.
Solution Approach 2:
The patent employs composite material strategies by selecting from multiple high-k dielectric materials (AlN, Si3N4, TiO2, etc.) that can be combined or selected based on specific requirements. This allows optimizing both the electrical coupling properties and the bonding characteristics simultaneously.
2Reliability
If the thickness of the buried insulating layer is reduced to reduce parasitic electrostatic fields, then short channel effects are mitigated, but current leakage increases
Solution Approach 1:
By changing the dielectric constant parameter to higher values, the patent achieves better electrostatic field control (reducing short channel effects) while maintaining a thicker physical layer that provides better insulation and reduces current leakage to the substrate.
3Reliability
If the thickness of the buried insulating layer is reduced to enhance coupling, then gate-channel coupling improves, but bonding defects increase
Solution Approach 1:
The patent applies parameter change by increasing the dielectric constant of the insulating layer material. This allows achieving the desired gate-channel coupling (capacitance) with a thicker layer, which in turn reduces bonding defects and improves overall manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the coupling between the gate and transistor channel while maintaining a sufficient insulating layer thickness for robust bonding, reducing parasitic effects and manufacturing defects, thereby improving the yield and quality of SOI or SeOI structures.
Implementation Method 1
a buried insulating layer made of high k type dielectric materials with a dielectric constant greater than silicon dioxide... materials like AlN, Si3N4, or TiO2, which have a capacitance equivalent to a silicon dioxide layer
Implementation Method 2
bonding the face of the donor substrate with a face of the receiving substrate by molecular adhesion
Implementation Method 3
implanting atomic species under a face of a semiconductor substrate (for ex., Si or SiGe), in an implantation zone
Implementation Method 4
cleaving the donor substrate at the level of the implantation zone to transfer the part of the substrate situated between the surface subjected to implantation on the receiving substrate, and the implantation zone corresponding to the active layer
Data Source
AI summary
The invention relates to semiconductor-on-insulator structure and its method of manufacture. This structure includes a substrate, a thin, useful surface layer and an insulating layer positioned between the substrate and surface layer. The insulating layer is at least one dielectric layer of a high k material having a permittivity that is higher than that of silicon dioxide and a capacitance that is substantially equivalent to that of a layer of silicon dioxide having a thickness of less than or equal to 30 nm.