High-k Inner Spacer Protection for GAA S/D Etch Damage

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Solution Overview

Problem

The formation of nanostructure channels in semiconductor devices, such as GAA FETs, can cause damage to the source/drain epitaxial structures due to etchant gases, leading to increased surface roughness and reduced device performance.

Innovation Solution

A protection layer made of high-k dielectric material, such as hafnium oxide, is applied to the inner spacer structures to prevent etching and protect the S/D epitaxial structures during the formation of nanostructure channels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If etchant gases are used to form nanostructure channels, then nanostructure channels are formed, but source/drain epitaxial structures are damaged with increased surface roughness

Engineering Contradiction:

Improvenanostructure channel formationVSAvoidsurface roughness of S/D epitaxial structures

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

A protection layer made of high-k dielectric material (such as hafnium oxide) is introduced as an intermediary between the etchant gases and the source/drain epitaxial structures. This protection layer absorbs the harmful etching action while allowing the nanostructure channel formation to proceed, thereby preventing damage to the S/D epitaxial structures and maintaining surface smoothness.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If protection layer is added to protect inner spacer structures, then damage to S/D epitaxial structures is reduced, but device complexity increases

Engineering Contradiction:

Improveprotection of S/D epitaxial structuresVSAvoidstructure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The protection layer utilizes high-k dielectric material with specific material parameters (high dielectric constant) to achieve effective protection. By selecting materials with appropriate dielectric properties, the layer provides robust protection against etching while maintaining compatibility with existing device structures and minimizing overall complexity.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The protection layer reduces damage to the S/D epitaxial structures by 75% to 95% and improves device performance by 5% to 10% compared to devices without the protection layer.

Implementation Method 1

Methodology Applied

Scientific EffectEtching resistance:

Data Source

PatentUS20250366132A1Spacer structures for semiconductor devices

Publication Date: 2025.11.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

The present disclosure describes a semiconductor device having a protection layer on inner spacer structures. The semiconductor device includes a nanostructure on a substrate. The nanostructure includes multiple semiconductor layers. The semiconductor device further includes a gate structure wrapped around a middle portion of the multiple semiconductor layers and a spacer structure adjacent to an end portion of the multiple semiconductor layers. The gate structure includes a high-k dielectric layer. The semiconductor device further includes a protection layer between the high-k dielectric layer and the spacer structure.