Histogram Calculation Apparatus Dynamic Memory Mapping
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Solution Overview
Problem
Existing methods for calculating characteristic amounts based on histograms face inefficiencies due to fixed mappings between histogram bins and memory spaces, limiting parallelization and memory usage, which slows down the calculation process.
Innovation Solution
A calculation apparatus that dynamically generates tables to map buffer positions to memory addresses, allowing parallel access to multiple memory banks, thereby optimizing the distribution of data and enhancing processing speed through parallelization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a fixed mapping between histogram bins and memory addresses is used, then the memory structure is simple, but the parallelization efficiency and processing speed decrease
Solution Approach 1:
The patent applies dynamics by making the memory mapping flexible rather than fixed. The mapping between histogram bins and memory addresses is dynamically adjusted based on data distribution characteristics, allowing the system to adapt to different scenarios and maximize parallelization efficiency while maintaining reasonable structural complexity
Solution Approach 2:
The patent changes the mapping parameter from a fixed address assignment to a dynamic one that considers data characteristics. By adjusting the mapping strategy based on histogram bin distribution and memory bank availability, the system improves parallel processing capability without significantly increasing overall system complexity
2Ease of operation
If random access to memory is used for vote process, then the memory access is flexible, but parallel calculation cannot be achieved and processing speed decreases
Solution Approach 1:
The patent segments the memory into multiple banks and divides the histogram bins across these banks. This segmentation enables parallel access to different memory banks by different processing units, transforming the sequential random access into parallel access operations and significantly improving calculation speed while maintaining access flexibility
Solution Approach 2:
The patent introduces a new dimension of parallelization by organizing memory access in terms of memory banks and processing units working simultaneously. This dimensional transformation from sequential access to parallel access across multiple dimensions (banks, processors, bins) enables rapid calculation while preserving operational flexibility
3Productivity
If memory is divided into multiple banks for parallel access, then processing speed improves, but the efficiency of memory space usage decreases
Solution Approach 1:
The patent uses dynamic mapping strategies that adapt to the actual data distribution across histogram bins. This dynamic approach ensures that memory banks are utilized efficiently based on real-time needs, preventing waste of memory space while maintaining high parallel processing speeds
Solution Approach 2:
The patent applies different mapping strategies to different regions of the histogram based on local data characteristics. High-frequency bins may be mapped to frequently accessed memory locations while low-frequency bins use other locations, optimizing both memory utilization and processing speed locally across different parts of the histogram
Data Source
AI summary
A calculation apparatus for amount of characteristic that calculates an amount of characteristic based on a histogram of an amount of characteristic of input data includes: a buffer for holding a portion of the input data; a memory, having a plurality of banks, for holding calculation results of the histogram; a generation unit for generating a table in which a position of a target data on the buffer of which the amount of characteristic is to be calculated corresponds to a position on the memory to which a category of the calculated amount of characteristic is voted; and a vote unit that determines a category of the amount of characteristic of the target data and that performs a vote to the position on the memory shown on the table.