Histogram Statistics Circuit Parallel Bank Segmentation
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Solution Overview
Problem
Conventional multimedia processing systems face performance bottlenecks and power consumption issues due to the inefficiency of histogram statistics in high-resolution image processing, particularly with vector processors that struggle to handle large pixel counts in real-time applications.
Innovation Solution
A histogram statistics circuit is designed with a counter cache, controller, parsing circuit, matching-and-decoding circuit, and count value updating circuit to group pixels and update counters in parallel, allowing multiple pixels to be processed in one clock cycle, reducing ineffective operations and improving computing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a memory-based histogram statistics circuit is used to store 256 statistical count values, then the circuit can complete histogram statistics for high-resolution pictures, but the computing performance cannot meet real-time processing requirements due to memory port limitations
Solution Approach 1:
The patent divides the 256 statistical count values into multiple banks (e.g., 4 banks with 64 counters each), allowing parallel access to different memory banks through multiple ports. This segmentation enables simultaneous reading and writing operations across different banks, increasing throughput without requiring each individual counter to have dedicated ports.
Solution Approach 2:
The patent introduces a bank selection dimension in addition to the counter index dimension. Instead of accessing a single linear array of 256 counters through limited ports, the system adds a bank selection signal that routes access to different memory banks, effectively creating a two-dimensional address space that enables parallel operations.
2Productivity
If a vector processor is used to repeatedly fetch 256 statistics counters for two million pixels, then histogram statistics can be completed, but an obvious fetch bottleneck and computing performance bottleneck occurs
Solution Approach 1:
The patent pre-organizes the 256 counters into multiple banks that can be accessed in parallel. Before processing begins, the counter array is structured into banks with associated decode logic ready to simultaneously generate multiple counter addresses from a single pixel value, eliminating the need for sequential fetching during the actual processing phase.
Solution Approach 2:
The patent creates multiple copies of counter storage structures across different banks, each capable of independent access. Instead of having a single copy of 256 counters that must be accessed sequentially, the system maintains parallel copies distributed across banks, allowing simultaneous access through multiple ports without interference.
3Productivity
If the memory has only 2 read ports and 2 write ports, then the memory structure is simple, but the histogram statistics circuit can collect statistics of only one or two pixels in one clock cycle
Solution Approach 1:
The patent segments the single memory structure into multiple banks (e.g., 4 banks), each with its own read and write ports. This segmentation allows the system to process multiple pixels simultaneously by directing different pixel operations to different banks, effectively multiplying the processing capacity without requiring a single complex monolithic memory.
Solution Approach 2:
The patent combines multiple simpler memory banks into a unified histogram statistics circuit system. Each bank is a relatively simple memory structure, but when merged and coordinated through the control logic and bank selection mechanism, they collectively provide high-throughput parallel processing capability that exceeds what a single complex memory could achieve.
Data Source
AI summary
A histogram statistics circuit and a multimedia processing system, where the multimedia processing system includes a memory, a histogram statistics circuit, and a processor. The memory is configured to store multimedia data. The histogram statistics circuit is configured to obtain the multimedia data from the memory and perform histogram statistics on the multimedia data, to generate a statistical result. The processor is configured to process the multimedia data based on the statistical result and a histogram application algorithm.