Hitless Clock Switching with Phase Pre-Compensated Backup Reference
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Solution Overview
Problem
Conventional hitless clock switching systems require multiple phase-locked loops, leading to increased area, power consumption, and complexity, which can result in phase jitter and instability during reference clock switching, affecting communication network stability.
Innovation Solution
A system and method utilizing a sampling circuitry group, phase detector group, compensator group, signal selector, and phase-locked loop to sample and process reference clock signals, generating a backup reference clock signal to ensure stable clock switching without the need for multiple phase-locked loops, thereby reducing system complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple phase-locked loops are used for reference clock synchronization and phase adjustment, then clock switching reliability is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent merges the functions of multiple phase-locked loops into a single phase-locked loop by pre-compensating the secondary reference clock signal. The compensator group calculates phase differences between primary and secondary reference clocks and adjusts the secondary clock's phase in advance, allowing one phase-locked loop to handle both synchronization and phase adjustment tasks that previously required three separate loops.
Solution Approach 2:
The patent applies preliminary action by pre-compensating the phase of the secondary reference clock signal before switching occurs. The compensator group continuously monitors and adjusts the secondary clock's phase to match the primary clock, so that when switching happens, no phase jitter occurs. This eliminates the need for a separate phase adjustment loop after switching.
2Reliability
If multiple phase-locked loops are used for clock synchronization, then phase stability is improved, but area and power consumption increase
Solution Approach 1:
The patent combines the functionality of three phase-locked loops into one by using a compensator group to pre-adjust the secondary reference clock's phase. This single phase-locked loop then handles both the synchronization and phase alignment tasks, reducing power consumption while maintaining phase stability during clock switching.
3Reliability
If multiple phase-locked loops are used for reference clock processing, then clock switching reliability is improved, but system area increases
Solution Approach 1:
The patent merges three separate phase-locked loop circuits into a single phase-locked loop by introducing a compensator group that pre-processes the secondary reference clock signal. This integration significantly reduces the silicon area required while maintaining the reliability of hitless clock switching through phase pre-compensation.
Data Source
AI summary
A system and a method for hitless clock switching are provided. In the system, a sampling circuitry group samples a primary reference clock signal and a secondary reference clock signal to obtain first and second sampling information, respectively. A phase detector group obtains a phase difference between the primary and secondary reference clock signals with the first and second sampling information. A compensator group adds the phase difference to a phase of the secondary reference clock signal to obtain a backup reference clock signal. When the primary reference clock signal is abnormal or missing, the signal selector determines the backup reference clock signal as a target reference clock signal and sends it to a phase-locked loop. The phase-locked loop performs loop control on the target reference clock signal, thereby implementing hitless switching of reference clock signals.