Normally-off HJFET Gate Blocking Stack for Leakage Control
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Solution Overview
Problem
Thin-film heterojunction field-effect transistors (HJFETs) with crystalline silicon channels and plasma-enhanced chemical vapor deposition (PECVD) contact regions face challenges in achieving stable drive currents for high-resolution active-matrix organic light-emitting diode displays due to high gate leakage when the gate heterojunction is forward-biased, limiting their application to normally-ON transistors.
Innovation Solution
Incorporating a blocking stack, such as an n+ a-Si:H/i a-Si:H diode, into the gate stack of HJFETs to suppress gate current at forward bias, allowing for the formation of normally-OFF devices and integration with MOSFETs on the same substrate, enabling complementary circuits and low-temperature processing on large-area electronics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a heterojunction gate structure is used in thin-film transistors, then manufacturing cost and processing temperature are reduced, but gate leakage current increases when the gate heterojunction is forward-biased
Solution Approach 1:
The gate structure is segmented into multiple functional layers: a heterojunction gate for low-temperature manufacturing, a blocking stack (comprising an intrinsic layer and a doped layer) for suppressing gate leakage, and a Schottky junction for enabling normally-off operation. Each layer performs a specific function to collectively resolve the contradiction between ease of manufacture and gate leakage control.
Solution Approach 2:
The gate employs a composite structure combining different material systems: amorphous silicon heterojunction for low-temperature processing, intrinsic and doped semiconductor layers for leakage blocking, and metal contacts for Schottky junction formation. This composite approach integrates the advantages of each material system to achieve both manufacturability and electrical performance.
2Temperature
If conventional heterojunction transistors are used, then low-temperature processing is achieved, but normally-off operation cannot be implemented due to high gate leakage
Solution Approach 1:
The blocking stack is designed with predetermined doping concentrations and layer thicknesses to create built-in potential barriers that preemptively suppress gate leakage current before it can compromise normally-off operation. The Schottky junction is engineered with specific barrier heights to establish the required threshold voltage for normally-off behavior, preventing leakage-induced failure of the normally-off mode.
Solution Approach 2:
The gate structure utilizes controlled variations in doping concentrations, layer thicknesses, and material compositions to tune the electrical characteristics. By adjusting these parameters, the device achieves both low-temperature processing compatibility and the electrical properties necessary for normally-off operation, resolving the contradiction between temperature and reliability.
3Reliability
If crystalline materials are used for high drive current stability, then device performance improves, but processing cost increases and large-area processing becomes difficult
Solution Approach 1:
The transistor channel region is formed using crystalline semiconductor material (such as polysilicon or single-crystal silicon) to ensure high drive current stability and device performance. The gate and contact regions use amorphous silicon and other materials that enable low-temperature, large-area processing. This local differentiation of material quality allows each region to optimize its properties for its specific function while maintaining overall manufacturability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The blocking stack effectively reduces gate current, enabling normally-OFF HJFET devices with MOSFET-like characteristics, suitable for high-resolution displays and large-area electronics, while maintaining compatibility with existing deposition techniques and reducing the need for high-temperature substrate processing.
Implementation Method 1
Incorporating a blocking stack, such as an n+ a-Si:H/i a-Si:H diode, into the gate stack of HJFETs to suppress gate current at forward bias
Implementation Method 2
The gate region includes at least one Schottky junction
Implementation Method 3
thin-film heterojunction field-effect transistors (HJFETs) with crystalline silicon channels and plasma-enhanced chemical vapor deposition (PECVD) contact regions
Data Source
AI summary
A junction field-effect transistor (JFET) with a gate region that includes two separate sub-regions having material of different conductivity types and/or a Schottky junction that substantially suppresses gate current when the gate junction is forward-biased, as well as complementary circuits that incorporate such JFET devices.