HKMG Gate-Last Metal Stack Work Function Tuning
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Solution Overview
Problem
The integration of high k dielectric material and metal gate stacks for nMOS and pMOS transistors faces challenges such as poor performance of pMOS transistors and the inability to tune work functions independently, leading to suboptimal semiconductor device performance.
Innovation Solution
A method is developed to form metal gate stacks for nFETs and pFETs with different compositions and configurations, involving the formation of high k dielectric material layers, metal layers, and polysilicon layers, followed by chemical mechanical polishing and etching processes to create gate trenches and fill them with metal materials, allowing independent tuning of work functions and optimization of nMOSFET and pMOSFET performances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single metal gate stack configuration is used for both nMOS and pMOS transistors, then the manufacturing process is simplified, but the work functions cannot be tuned independently and device performance deteriorates
Solution Approach 1:
The patent applies local quality by forming different metal gate stack configurations in different regions of the semiconductor device. Specifically, nMOS regions receive a first metal gate stack with a first work function, while pMOS regions receive a second metal gate stack with a second work function. This allows each transistor type to have optimized local electrical characteristics while maintaining a unified manufacturing process flow.
Solution Approach 2:
The patent segments the metal gate formation process into region-specific steps. After forming a common high-k dielectric layer across the entire substrate, the metal layer formation is segmented into selective regions using patterning techniques. This enables independent work function tuning for nMOS and pMOS transistors through separate metal deposition and etching processes performed on different device regions.
2Reliability
If metal gate stacks are formed with different compositions for nMOS and pMOS, then work functions can be tuned independently, but the process complexity increases
Solution Approach 1:
The patent employs preliminary action by forming a complete metal gate stack structure across the entire substrate before performing any selective removal. A uniform metal layer is deposited over the whole wafer, then patterning and etching processes selectively remove metal from specific regions to create the desired nMOS and pMOS configurations. This approach simplifies process control compared to forming different metal layers sequentially.
Solution Approach 2:
The patent utilizes parameter changes by modifying the metal gate stack composition and thickness parameters in different device regions. By controlling metal layer thickness, material composition, and removal depth through etching, the work function parameter is tuned independently for nMOS and pMOS transistors. This allows continuous adjustment of electrical characteristics without fundamentally changing the process architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance of both nMOSFETs and pMOSFETs by forming metal gate stacks with specific layer configurations, addressing the issues of previous metal gate formation methods and improving device performance.
Implementation Method 1
applying a first chemical mechanical polishing (CMP) process to the semiconductor substrate
Implementation Method 2
removing the polysilicon from the first dummy gate, resulting in a first gate trench
Data Source
AI summary
The present disclosure provides a method for making metal gate stacks of a semiconductor device. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a conductive material layer on the high k dielectric material layer; forming a dummy gate in a n-type field-effect transistor (nFET) region and a second dummy gate in a pFET region employing polysilicon; forming an inter-level dielectric (ILD) material on the semiconductor substrate; applying a first chemical mechanical polishing (CMP) process to the semiconductor substrate; removing the polysilicon from the first dummy gate, resulting in a first gate trench; forming a n-type metal to the first gate trench; applying a second CMP process to the semiconductor substrate; removing the polysilicon from the second dummy gate, resulting in a second gate trench; forming a p-type metal to the second gate trench; and applying a third CMP process to the semiconductor substrate.