HKMG Gate Barrier Nitridation for Multi-Vt Semiconductor Structures
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Solution Overview
Problem
As semiconductor technology advances, the challenge of achieving multiple threshold voltage (Vt) designs in integrated circuits becomes complex due to the limitations of gate length scaling and the need for effective gate metal materials, particularly in high-voltage devices where Al-diffusion barriers are required, while maintaining competitive gap-filling abilities.
Innovation Solution
The method involves forming semiconductor structures using an HKMG process with in-situ and/or ex-situ nitridation of barrier layers with varying nitrogen concentrations to create N-containing barrier layers that enhance Al-diffusion barrier abilities, allowing for the formation of multiple-Vt structures suitable for different voltage devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If gate length is scaled down to improve device performance, then device speed and integration density are improved, but manufacturing complexity increases and multiple threshold voltage design becomes difficult
Solution Approach 1:
The patent applies local quality by forming different barrier layer structures in different regions of the semiconductor device. Specifically, a first barrier layer structure is formed in a first region and a second barrier layer structure is formed in a second region, allowing different threshold voltage characteristics to be achieved in different areas of the same device, thus enabling multiple-Vt design without increasing overall manufacturing complexity
Solution Approach 2:
The barrier layer is segmented into multiple distinct structures (first barrier layer structure and second barrier layer structure) with different compositions and properties. This segmentation allows independent optimization of threshold voltage characteristics for different device regions while maintaining a unified manufacturing process flow
2Ease of manufacture
If barrier layer thickness is reduced to maintain gap-filling ability, then manufacturing ease is improved, but Al-diffusion barrier effectiveness deteriorates
Solution Approach 1:
The patent employs composite materials by creating barrier layer structures with different compositions - the first barrier layer structure contains a different material composition than the second barrier layer structure. This composite approach allows each layer to be optimized for specific functions: one layer provides excellent gap-filling while the other provides superior Al-diffusion blocking, resolving the contradiction between manufacturability and reliability
Solution Approach 2:
The patent changes material composition parameters of the barrier layer structures to achieve different properties. By adjusting the composition of the first and second barrier layer structures, the patent optimizes both the gap-filling ability (manufacturability) and Al-diffusion barrier effectiveness (reliability) without requiring increased thickness
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively mitigates Al diffusion into high-k gate dielectric layers, even with thin barrier layers, and maintains competitive gap-filling abilities, enabling the fabrication of semiconductor structures suitable for both high-voltage and low-voltage devices with improved performance.
Implementation Method 1
N-containing barrier layers that enhance Al-diffusion barrier abilities
Implementation Method 2
in-situ and/or ex-situ nitridation of barrier layers with varying nitrogen concentrations
Data Source
AI summary
A method for forming a semiconductor structure includes forming a first FET device and a second FET device over a substrate. Forming a first gate trench in the first FET device and a second gate trench in the second FET device. Forming a first high-k gate dielectric layer in the first gate trench, and a second high-k gate dielectric layer in the second gate trench. Forming a first barrier layer over the first high-k gate dielectric layer, and a second barrier layer over the second high-k gate dielectric layer. Increasing N nitridations in the first and second barrier layers. Removing the second barrier layer to expose the second high-k gate dielectric layer. Forming a first work function metal layer over the first barrier layer and a second work function metal layer over the second high-k gate dielectric layer.