HKMG Boundary Structure for High-Voltage and Low-Voltage Integration
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Solution Overview
Problem
Integrated circuits with high-k metal gate (HKMG) technology face challenges in embedding high voltage devices and low voltage devices due to boundary defects, contamination from gate dielectric residues, and uneven surfaces caused by planarization processes, which affect device performance and manufacturing complexity, especially at advanced process nodes like 28 nm and beyond.
Innovation Solution
A boundary structure is introduced in the boundary region between low voltage and high voltage regions, comprising an isolation structure, a first polysilicon component, a boundary dielectric layer, and a second polysilicon component with slanted sidewalls to minimize residue contamination and provide structural support, reducing isolation damage and dishing effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high voltage devices and low voltage devices are integrated on the same chip using HKMG technology, then functional density and device performance are improved, but boundary defects and contamination from gate dielectric residues occur at the interface between high voltage and low voltage regions
Solution Approach 1:
The chip is divided into distinct high voltage and low voltage regions with a clearly defined boundary structure. The gate dielectric layers are segmented into a first gate dielectric layer for high voltage devices and a second gate dielectric layer for low voltage devices, preventing mixing and contamination at the interface while maintaining high functional density through spatial separation.
Solution Approach 2:
Different gate dielectric layer configurations are applied to different regions of the chip: a first gate dielectric layer with specific properties is used in the high voltage region, while a second gate dielectric layer with different properties is used in the low voltage region. This local differentiation allows each region to be optimized for its specific voltage requirements while preventing cross-contamination at the boundary.
2Shape
If planarization processes are used to integrate high voltage and low voltage devices, then surface uniformity is improved, but dishing effects and isolation damage occur
Solution Approach 1:
A boundary structure is formed in advance at the interface between high voltage and low voltage regions before completing the planarization process. This preliminary boundary structure acts as a protective framework that prevents dishing effects and isolation damage from occurring during subsequent planarization steps, while still achieving the desired surface uniformity for device operation.
3Ease of manufacture
If gate dielectric layers are patterned and removed during manufacturing, then device integration is achieved, but residue contamination and isolation damage increase
Solution Approach 1:
The gate dielectric layers are segmented into distinct first and second layers for high and low voltage regions respectively. This segmentation allows selective patterning and removal of the second gate dielectric layer in the low voltage region without affecting the first gate dielectric layer in the high voltage region, thereby reducing residue contamination and isolation damage while maintaining ease of manufacture.
Solution Approach 2:
The second gate dielectric layer in the low voltage region is selectively extracted or removed after the boundary structure is formed. This extraction process is performed in a controlled manner that prevents residue contamination and isolation damage, while still achieving the necessary device integration and functionality.
Data Source
AI summary
The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed directly on an upper surface of the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.