High-K Metal Gate Stack Integration for CMOS Core and IO Regions
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Solution Overview
Problem
Integration issues arise when forming various high-k/metal-gate (HK/MG) field effect transistors (FETs) on a single IC chip, such as HK/MG p-type FET core, n-type FET core, input/output nFET, input/output pFET, and high-resistor, due to the complexity of scaling down in semiconductor manufacturing.
Innovation Solution
A method for fabricating semiconductor devices with various gate stacks involves forming a semiconductor substrate with doped regions and isolation features, followed by sequential deposition and patterning of dielectric layers, capping layers, and work function metal layers, allowing for flexible integration of different HK/MG structures by altering the sequence of capping layer deposition and patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional scaling down process is used to reduce geometry size, then production efficiency increases and costs decrease, but processing complexity increases
Solution Approach 1:
The fabrication process is divided into separate sequence groups (first sequence and second sequence) that can be independently selected and executed. Each sequence represents a distinct fabrication pathway with different deposition and patterning steps, allowing the complex integration process to be managed through modular, selectable segments rather than a single monolithic process flow.
Solution Approach 2:
The patent implements dynamic process selection where the fabrication sequence can be adapted based on device type requirements. Different FET types (p-type, n-type, input/output, high-resistor) can select from different sequence combinations, making the process flexible and adaptable rather than static and rigid.
2Productivity
If various HK/MG FET structures are integrated onto a single IC chip, then functional density increases, but integration issues and process complexity increase
Solution Approach 1:
Different regions of the IC chip can utilize different fabrication sequences tailored to their specific device requirements. Core regions, input/output regions, and high-resistor regions can each be processed with the sequence most appropriate for their functional needs, allowing local optimization without compromising the entire chip integration.
Solution Approach 2:
The patent creates a universal fabrication framework that can handle multiple FET types (p-type, n-type, input/output, high-resistor) and various HK/MG structures through a common set of selectable sequences. This multi-functional approach allows a single integrated process system to accommodate diverse device architectures.
3Adaptability or versatility
If flexible fabrication process is implemented to accommodate various HK/MG structures, then adaptability increases, but process complexity increases
Solution Approach 1:
The patent establishes preliminary process frameworks with predefined sequence groups that capture common fabrication patterns for different device types. By preparing these sequence templates in advance, the system achieves flexibility through pre-configured options rather than requiring complex real-time process decisions, reducing the perceived complexity while maintaining adaptability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient and flexible fabrication of multiple gate stacks, facilitating the integration of CMOS devices with Core/IO/Resistors while maintaining reasonable threshold voltages for NMOS and PMOS, addressing the complexity of integrating diverse HK/MG FETs on a single chip.
Implementation Method 1
depositing a capping layer of a second material on the HK dielectric layer
Implementation Method 2
depositing a capping layer of a second material on the HK dielectric layer
Data Source
AI summary
A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.