SOI HKMG Gate Layout for Low- and High-Voltage Memory Integration
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Solution Overview
Problem
Existing SOI-based HKMG transistors face challenges in integrating low-voltage and high-voltage applications on the same substrate due to dishing effects during polishing, which affects the integration of other devices like memory arrays operating under high voltage.
Innovation Solution
The integration of high-voltage transistors with multiple HKMG structures functioning as dummy gate structures prevents dishing effects during polishing, allowing for the concurrent formation of low-voltage and high-voltage transistors on a single silicon-on-insulator substrate, enabling the integration of memory arrays that can operate under high voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional SOI-based HKMG transistor fabrication is used, then low-voltage transistors can be formed, but dishing effects occur during polishing that prevent integration of high-voltage transistors and memory arrays on the same substrate
Solution Approach 1:
The substrate is divided into first and second areas with different transistor configurations. The first area contains conventional low-voltage transistors, while the second area contains high-voltage transistors with additional dummy gate structures. This segmentation allows each area to be optimized for its specific voltage requirement while maintaining overall substrate compatibility.
Solution Approach 2:
Dummy gate structures are introduced as intermediary elements in the high-voltage transistor area. These dummy gates act as placeholders that maintain the necessary gate structure during fabrication and prevent dishing effects during polishing, enabling subsequent formation of functional high-voltage transistors and memory arrays.
2Adaptability or versatility
If multiple device types are integrated on the same substrate, then device versatility increases, but the polishing process creates dishing effects that degrade manufacturing precision
Solution Approach 1:
Different gate structures are implemented in different areas of the substrate. The first area uses conventional gate structures optimized for low-voltage operation, while the second area uses gate structures with dummy gates optimized for high-voltage operation and polishing stability. This local differentiation allows each region to have properties tailored to its specific function.
Data Source
AI summary
A semiconductor device includes a lower silicon layer comprising a first area and a second area. The lower silicon layer in the first area includes a first silicon oxide layer, a first upper silicon layer disposed above the first silicon oxide layer, and a first metal gate disposed above the first upper silicon layer. The lower silicon layer in the second area includes a second silicon oxide layer, a plurality of first doped silicon gates disposed above the second silicon oxide layer, and a plurality of portions of a second doped silicon gate disposed above the second silicon oxide layer. The plurality of first doped silicon gates and the plurality of portions of the second doped silicon gate are alternatively arranged with each other. The lower silicon layer in the second area also includes a plurality of second metal gates disposed directly above the plurality of first doped silicon gates, respectively.