HKMG Gate Dielectric Thickness Control for I/O and Core Devices
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Solution Overview
Problem
The integration of high-K metal gate (HKMG) process for core devices with the fabrication process of peripheral I/O devices in semiconductor manufacturing is challenging due to the difficulty in simultaneously forming gate dielectric layers with different thickness requirements, as the HKMG process requires a thin interface layer for core devices and a thicker gate dielectric layer for I/O devices, which is hard to achieve using conventional thermal or chemical oxidation processes without affecting the structure of sources and drains.
Innovation Solution
A method is developed to fabricate integrated semiconductor devices by forming a thicker first gate dielectric layer for I/O devices before forming sources and drains, and a thinner second gate dielectric layer for core devices, using a combination of thermal oxidation and chemical mechanical polishing to ensure the correct thickness and integration of both layers, allowing for the formation of high-K dielectric and metal gates in trenches with minimal thermal budget impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick gate dielectric layer is formed for I/O devices, then the leakage current is reduced, but the interface layer thickness for core devices becomes insufficient
Solution Approach 1:
The gate dielectric layer is segmented into two distinct layers: a first gate dielectric layer for I/O devices and a second gate dielectric layer for core devices. This segmentation allows each layer to be optimized independently - the first layer can be thick to reduce leakage in I/O devices, while the second layer can be thin to provide proper interface for core devices, thus resolving the contradiction between leakage reduction and interface layer thickness control
Solution Approach 2:
Different regions of the semiconductor device are assigned different gate dielectric layer configurations. I/O device regions receive a thick first gate dielectric layer for low leakage, while core device regions receive a thin second gate dielectric layer for proper interface quality. This local differentiation allows each region to have the optimal dielectric thickness for its specific function, resolving the contradiction between global leakage reduction and local interface requirements
2Ease of manufacture
If conventional thermal or chemical oxidation processes are used to form gate dielectric layers, then the dielectric layers can be formed, but the structure of sources and drains is affected
Solution Approach 1:
The first gate dielectric layer is formed using thermal or chemical oxidation processes before the sources and drains are created. By performing this oxidation action preliminarily, the gate dielectric layer is established while the sources and drains are still in their initial state, avoiding the thermal budget impact that would otherwise damage the already-formed source and drain structures. This preliminary timing resolves the contradiction between ease of manufacture and source/drain structure quality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the simultaneous formation of gate dielectric layers with the required thickness for both I/O and core devices, ensuring the dielectric constant matching and maintaining the quality of sources and drains, thus integrating the HKMG process with I/O device fabrication effectively.
Implementation Method 1
using a combination of thermal oxidation and chemical mechanical polishing to ensure the correct thickness and integration of both layers
Implementation Method 2
using a combination of thermal oxidation and chemical mechanical polishing to ensure the correct thickness and integration of both layers
Data Source
AI summary
A method is provided for fabricating an integrated semiconductor device. The method includes providing a semiconductor substrate having a first active region, a second active region and a plurality of isolation regions; forming a first gate dielectric layer on one surface of the semiconductor substrate; and forming a plurality of substituted gate electrodes, a layer of interlayer dielectric and sources/drains. The method also includes forming a first trench and a second trench; and covering the first gate dielectric layer on the bottom of the first trench. Further, the method includes removing the first dielectric layer on the bottom of the second trench; subsequently forming a second gate dielectric layer on the bottom of the second trench; and forming metal gates by filling the first trench and second trench using a high-K dielectric layer, followed by completely filling the first trench and the second trench using a gate metal layer.