HKMG Gate Stack Nitridation for Stable PMOS Threshold Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The current HKMG process in semiconductor manufacturing, particularly at nodes below 28 nm, faces challenges due to lateral diffusion of metal elements affecting the electrical properties of PMOS transistors, leading to increased threshold voltage and complexity in manufacturing processes.
Innovation Solution
A method involving decoupled plasma nitridation and post-nitridation annealing at controlled temperatures to reduce oxygen vacancies in the high dielectric constant layer, followed by forming P-type and N-type work function metal layers, with dipoles fixing laterally diffused metals to minimize threshold voltage fluctuations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional HKMG process is used for manufacturing, then metal gate structure can be formed, but lateral diffusion of metal elements occurs causing increased PMOS threshold voltage and manufacturing complexity
Solution Approach 1:
The patent applies preliminary action by performing decoupled plasma nitridation and post-nitridation annealing on the high dielectric constant layer before metal layer formation. This preliminary treatment reduces oxygen vacancies in the dielectric layer, which prevents lateral diffusion of metal elements during subsequent processing, thereby controlling threshold voltage before the manufacturing process begins.
Solution Approach 2:
The patent changes physical and chemical parameters of the high dielectric constant layer through controlled thermal annealing at specific temperatures (400-600°C) and plasma nitridation conditions. These parameter changes reduce oxygen vacancy concentration in the dielectric layer, thereby suppressing metal diffusion and stabilizing threshold voltage during manufacturing.
2Reliability
If metal layers are formed in HKMG structure, then work function adjustment is achieved, but lateral diffusion of metal affects electrical properties of PMOS
Solution Approach 1:
The patent converts the harmful effect of metal diffusion into a beneficial outcome by using controlled plasma nitridation and thermal annealing to create a modified dielectric layer. This layer allows controlled metal diffusion that forms beneficial dipole structures, which actually stabilize the threshold voltage rather than destabilize it, turning the harmful diffusion into a useful mechanism for electrical performance control.
Solution Approach 2:
The patent introduces plasma nitridation treatment and controlled thermal annealing as intermediary processes between dielectric layer formation and metal layer deposition. These intermediary treatments modify the dielectric layer's chemical and physical properties, creating a buffer zone that controls metal diffusion and prevents direct harmful interaction between metal layers and the PMOS channel.
3Manufacturing precision
If decoupled plasma nitridation and post-nitridation annealing are applied, then oxygen vacancies are reduced and metal diffusion is minimized, but additional process steps are added
Solution Approach 1:
The patent merges the decoupled plasma nitridation and post-nitridation annealing processes into an integrated treatment sequence that is performed together as a unified process module before metal deposition. This merging approach achieves the dual benefit of reducing oxygen vacancies and controlling metal diffusion while minimizing the total number of separate process steps and equipment transitions required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces the adverse impact of lateral metal diffusion on PMOS threshold voltage, improving electrical performance by maintaining stable threshold voltage and simplifying the manufacturing process.
Implementation Method 1
performing a decoupled plasma nitridation (DPN) process, the decoupled plasma nitridation process doping the high dielectric constant layer with nitrogen
Implementation Method 2
performing post nitridation anneal (PNA) on the high dielectric constant layer; a temperature of the post nitridation anneal is set below a first temperature, so as to reduce the number of oxygen vacancies in the high dielectric constant layer
Implementation Method 3
the laterally diffused metal is fixed at the oxygen vacancy in the high dielectric constant layer by forming dipoles
Data Source
AI summary
A method is disclosed for manufacturing a high dielectric constant metal gate of NMOS and PMOS, comprising: step 1, forming an interface layer; step 2, forming a high dielectric constant layer; step 3, performing decoupled plasma nitridation; step 4, performing plasma nitridation annealing with a temperature set below a preset first temperature to reduce the number of oxygen vacancies in the high dielectric constant layer; step 5, forming a P-type work function metal layer; step 6, removing the P-type work function metal layer from the region of the gate structure of the NMOS; step 7, forming an N-type work function metal layer, wherein metal atoms of the N-type work function metal layer of a first NMOS diffuses laterally from an interface to the P-type work function metal layer of adjacent first PMOS and are fixed at the oxygen vacancies by forming a dipole; and step 8, forming the metal gate.