HKMG Gate Structure Shielding Gate Oxide During SiGe Deposition
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Solution Overview
Problem
Current transistor manufacturing technologies face challenges in stabilizing the performance of transistors due to the miniaturization of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), particularly with the High-K Metal Gate (HKMG) technology, where the insulating property of the gate oxide layer is affected during the deposition of the germanium-silicon (SiGe) layer, leading to reduced electrical performance and reliability.
Innovation Solution
A method for manufacturing semiconductor devices involves forming a gate conductive layer that consistently covers the gate oxide layer, protecting it from damage during the formation of gate structures, and using the HKMG technology to reduce gate leakage and capacitance, thereby stabilizing the electrical performance of transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gate oxide layer is exposed during the formation of gate structures, then the manufacturing process is simplified, but the insulating property of the gate oxide layer is damaged
Solution Approach 1:
The gate conductive layer is formed to cover the gate oxide layer before the gate structure formation process begins. This preliminary protective action ensures that the gate oxide layer is not exposed to damage during subsequent manufacturing steps, while still allowing the gate structure to be formed over it.
Solution Approach 2:
The gate conductive layer serves as an intermediary protective layer between the gate oxide layer and the gate structure formation process. It protects the gate oxide layer from direct exposure to damaging processes while allowing the gate structure to be formed on top of it.
2Area of moving object
If the feature size of transistors is reduced, then the device density is improved, but the performance stability of transistors deteriorates
Solution Approach 1:
The invention changes the structural parameters of the gate by forming a gate conductive layer with specific material composition and thickness over the gate oxide layer. This parameter change allows the gate structure to function properly at reduced feature sizes while maintaining performance stability through the protective effect of the conductive layer.
3Reliability
If the HKMG technology is used to reduce gate leakage, then the electrical performance is improved, but the deposition process becomes more complex
Solution Approach 1:
The invention merges the gate oxide layer and gate conductive layer into a single integrated gate structure. This combination achieves the HKMG technology benefits of reduced gate leakage and capacitance while simplifying the overall deposition process by forming both layers in a unified manufacturing sequence rather than as separate complex processes.
Data Source
AI summary
A method for manufacturing a semiconductor device is provided. The method includes: a substrate is provided, the substrate being provided with a first device area and a second device area with different doping types; a gate oxide layer which covers the first device area and the second device area is formed; a gate conductive layer which covers the gate oxide layer is formed; a first gate structure is formed on the first device area, the first gate structure including the gate conductive layer and the gate oxide layer; a second gate structure is formed on the second device area, the second gate structure including the gate conductive layer and the gate oxide layer. In the first device area and the second device area, the gate conductive layer always covers the gate oxide layer.